{"id":2337642,"url":"https://alion.io/job/hcltech-design-lead-4","title":"Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":677},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-12T10:26:04Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-12T17:13:25Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nFull chip TB Architecture definition Experience writing ASIC/SoC testplans\nUVM based testbench development\n1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\nC based TB development\n1. Experience in developing TB components for SOC with C, SV\nTest case development, coding, execution, bug analysis\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\nGate Level Simulation\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis\nFunctional and Code Coverage closure\nparticipate in verification closure\nExperience in Perl/Shell scripting\nKey Responsibilities\nFull chip TB Architecture definitionExperience writing ASIC/SoC testplans\nUVM based testbench development\n1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\nC based TB development\n1. Experience in developing TB components for SOC with C, SV\nTest case development, coding, execution, bug analysis\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\nGate Level Simulation\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis\nFunctional and Code Coverage closure\nparticipate in verification closure\nExperience in Perl/Shell scripting\nSkill Requirements\nOther Requirements","description_format":"text","description_chars":2781,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-12T10:26:04Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":19,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-10-12T18:49:22Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-design-lead-4","json_url":"https://alion.io/job/hcltech-design-lead-4.json","meta":{"generated_at":"2026-10-12T18:49:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":30317,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-design-lead-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-design-lead-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-design-lead-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-design-lead-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-design-lead-4"}]}