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Location
In office
Seniority
Senior · 5+ years exp

Confirmed on the employer's own hiring board on Sep 25, 2026. First seen by Alion on Sep 25, 2026.

Overview
Company
Impact
Profile match
HCLTech is a major Indian multinational information technology (IT) services and consulting company headquartered in Noida, Uttar Pradesh. Spun off from the original HCL Group in 1991, it ranks as one of India's largest technology companies alongside firms like TCS, Infosys, and Wipro.

Job Summary

Candidates with 1.5 to 3 years' experience is mandatory

Good understanding of ASIC/SoC life cycle

Experience writing ASIC/SoC testplans

Experience in writing verification strategy document

UVM based testbench development:

Experience in ASIC/SoC Testbench definition

Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

Key Responsibilities

C based TB development:

Experience in developing TB components for SOC with C, SV

SV functional coverage, Assertions coding

1.Expertise & hands-on experience in OVM/UVM methodologies using SV

2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

Test case development, coding, execution, bug analysis :

1. Experience in developing TB components, including functional coverage implementation and assertion coding

2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.

4. Experience in SOC C based tests coding & debugging"

Skill Requirements

Gate Level Simulation:

Experience in Gate level simulation & netlist debugging

Regressions, coverage analysis

Experience in regression failure analysis

Functional and Code Coverage closure

Other Requirements

Core Technical Skills:-

Languages: Proficiency in Verilog, System Verilog, and core concepts of UVM.

Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.

EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).

Protocols: Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe).

Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

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