{"id":1223249,"url":"https://alion.io/job/hcltech-designer","title":"Designer","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-25T13:02:39Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-26T23:19:47Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Summary\nCandidates with 1.5 to 3 years' experience is mandatory\nGood understanding of ASIC/SoC life cycle\nExperience writing ASIC/SoC testplans\nExperience in writing verification strategy document\nUVM based testbench development:\nExperience in ASIC/SoC Testbench definition\nExperience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\nKey Responsibilities\nC based TB development:\nExperience in developing TB components for SOC with C, SV\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\nTest case development, coding, execution, bug analysis :\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\"\nSkill Requirements\nGate Level Simulation:\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis\nFunctional and Code Coverage closure\nOther Requirements\nCore Technical Skills:-\nLanguages: Proficiency in Verilog, System Verilog, and core concepts of UVM.\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nEDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).\nProtocols: Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe).\nScripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.","description_format":"text","description_chars":2105,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-09-25T13:02:39Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":23,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-09-26T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-designer","json_url":"https://alion.io/job/hcltech-designer.json","meta":{"generated_at":"2026-09-27T01:21:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1198,"day_limit":5000,"remaining_today":3802,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}