{"id":2929043,"url":"https://alion.io/job/hcltech-senior-design-lead-19","title":"Senior Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Design","role_family":"Design","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":140000,"max_usd":253000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":206},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-20T14:13:40Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T15:23:30Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nSubsystem RTL Integration Engineers to own complex SoC/subsystem integration, including RTL/IP integration, connectivity, CDC/RDC closure, RTL quality, and collaboration with Physical Design and Verification teams.\nKey Responsibilities\nOwn RTL integration at subsystem level, including integration of multiple IPs/functional blocks.\nImplement and validate IP-to-IP and subsystem connectivity, including clock, reset, control, and data interfaces.\nWork on Majellum-related integration and associated subsystem connectivity.\nPerform and drive closure of:\nCDC (Clock Domain Crossing)\nRDC (Reset Domain Crossing)\nRTL lint and structural/quality checks\nConnectivity checks\nDebug and resolve integration issues across multiple IP blocks.\nDefine and maintain clean RTL hierarchy and subsystem partitioning.\nWork closely with Physical Design (PD) teams on hierarchy, partitioning, implementation constraints, and integration requirements.\nCollaborate with RTL design, DV, DFT, architecture, and PD teams through subsystem integration and signoff.\nSupport design reviews, integration quality, issue tracking, and RTL readiness for downstream implementation.\nCDC/RDC, connectivity/static checks, debugging across IPs, and collaboration with physical design are also reflected in current SoC RTL integration roles.\nSkill Requirements\nStrong experience in ASIC/SoC RTL design and subsystem integration.\nStrong hands-on knowledge of Verilog/SystemVerilog.\nExperience integrating multiple IPs/subsystems into complex SoC designs.\nStrong understanding of connectivity, clocks, resets, CDC and RDC.\nExperience with Lint and RTL quality/signoff methodologies.\nGood understanding of RTL hierarchy and design partitioning.\nExperience working with Physical Design teams and understanding PD-driven hierarchy/partition requirements.\nStrong debugging and problem-solving skills.\nAbility to work across RTL, DV, DFT and PD teams.\nSystemVerilog, IP integration, CDC, lint closure, and cross-functional work with verification, PD, and DFT are typical requirements in RTL integration positions.\nOther Requirements\nExperience with Majellum or similar subsystem/integration environments.\nExperience with large, multi-clock/multi-reset SoCs.\nFamiliarity with synthesis, timing, low-power/UPF, DFT, and implementation flows.\nScripting knowledge in Tcl, Python, Perl, or Shell.\nExperience taking a subsystem from RTL integration through quality/signoff and PD handoff.","description_format":"text","description_chars":2449,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-20T14:13:40Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring 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