{"id":1223252,"url":"https://alion.io/job/hcltech-senior-design-lead-2","title":"Senior Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":["Mexico"],"countries":["MX"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":75000,"max_usd":173000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":677},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys SpyGlass","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-25T13:02:39Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-12T01:35:18Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":16},"description":"Job Summary\nB.Tech/ M.Tech with 6 to 8 years of experience exclusively in DFT.\nSub-system level: Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation.\nShould have expertise on Simulation debug No-timing/Timing.\nKey Responsibilities\n\"Sub-system level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation.\nThorough with Diagnostics and Repairability concepts.\nGood to have functional & integration knowledge of TAP controllers and JTAG.\nWorking knowledge of JTAG, iJTAG, ICL, PDL etc.\"\nSkill Requirements\n\"DFX and DFD feature insertion and verification at SS level.SOC level verification for the same.\nQC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc.\"\nCapable of doing SOC level verification, Pattern sim and delivery.\nShould be able to handle cluster team of 2-3 members.\nOther Requirements\nMust be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures.\nDesirable to have experience in Post Silicon Debug on Tester.\nGood at Communication. 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