{"id":3150285,"url":"https://alion.io/job/hcltech-senior-design-lead-22","title":"Senior Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Linux","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Synopsys ZeBu","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-23T11:53:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-28T23:54:52Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Summary\nWe are looking for a Senior Emulation Engineer with 7-10 years of experience in ASIC/SoC verification and emulation. The ideal candidate will have strong hands-on expertise in building, deploying, and debugging complex designs on hardware emulation platforms and accelerating pre-silicon verification for large-scale SoCs. Experience with advanced AI, Datacenter, Networking, Automotive, or HPC SoCs is highly desirable.\nKey Responsibilities\nKey Responsibilities\nDevelop, maintain, and optimize emulation environments for complex ASIC/SoC programs.\nPerform design bring-up, partitioning, compilation, and debug on emulation platforms.\nCollaborate with Design, Verification, Firmware, and Validation teams for pre-silicon verification activities.\nDebug emulation failures and analyze issues across RTL, testbench, and software stacks.\nEnable and execute SoC-level use cases, firmware boot, software regression, and system validation in emulation.\nDrive performance optimization of emulation runs, regression infrastructure, and debug workflows.\nSupport verification acceleration, HW/SW co-verification, and early software development.\nDevelop automation scripts and flows to improve emulation productivity and scalability.\nSkill Requirements\nRequired Skills\nStrong understanding of ASIC/SoC architecture and verification lifecycle.\nHands-on experience with industry-standard emulation platforms such as:\nCadence Palladium\nSynopsys ZeBu\nSiemens Veloce\nGood knowledge of Verilog/SystemVerilog and simulation-based verification methodologies.\nExperience with design partitioning, clocking strategies, probes, triggers, and emulation debug.\nStrong debugging skills across RTL, software, and system-level environments.\nExperience with Linux environments, scripting, and automation using Python, Perl, TCL, or Shell.\nFamiliarity with HW/SW co-verification and firmware-driven validation.\nOther Requirements\nHands-on emulation engineer with proven experience on Palladium, ZeBu, or Veloce, capable of handling large-scale SoCs and enabling early software execution, system validation, and verification acceleration for next-generation AI, Datacenter, Networking, Automotive, or HPC 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