{"id":3150287,"url":"https://alion.io/job/hcltech-senior-design-lead-23","title":"Senior Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Design","role_family":"Design","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":55000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":15},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence VIP","optional":true},{"name":"Cadence Xcelium","optional":true},{"name":"Formal Verification","optional":true},{"name":"Synopsys Verdi","optional":true}],"status":"live","first_seen_at":"2026-10-23T11:53:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-27T10:29:37Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Summary\nWe are seeking a Senior Design Verification Engineer with 8 to 15 years of experience in ASIC/SoC verification and deep expertise in one or more next-generation technologies such as PCIe Gen5/Gen6, LPDDR5/LPDDR6, HBM3/HBM4, UCIe, Ethernet, ARM Neoverse, CHI, and advanced SoC interconnects. The candidate will be responsible for developing robust verification environments, driving verification closure, and contributing to complex IP, subsystem, and SoC-level verification programs.\nKey Responsibilities\nKey Responsibilities\nDevelop and maintain reusable SystemVerilog/UVM based verification environments.\nCreate verification plans, test cases, sequences, scoreboards, and checkers.\nDevelop constrained-random and directed tests to validate complex protocol and architectural features.\nImplement functional coverage models and SystemVerilog Assertions (SVA).\nExecute regressions, analyze failures, and drive verification closure.\nDebug complex simulation failures and identify design versus testbench issues.\nCollaborate closely with Architecture, RTL Design, Firmware, and Validation teams.\nContribute to SoC-level integration and performance verification.\nRequired Skills\nStrong hands-on experience in SystemVerilog, UVM/OVM, Assertions (SVA), and Functional Coverage.\nSolid understanding of ASIC/SoC verification methodologies and verification lifecycle.\nExperience in protocol verification, testbench architecture, test development, and debug.\nKnowledge of C/C++ and scripting (Python/Perl/Shell/TCL).\nSkill Requirements\nNiche Expertise (One or More of the Following)\nHigh-Speed Interfaces & Memory\nPCIe Gen5/Gen6\nCXL 2.0/3.0\nUCIe\nLPDDR5/LPDDR6\nHBM2E/HBM3/HBM4\nDDR5\nEthernet (100G/400G/800G)\nUSB4\nMIPI (CSI/DSI)\nARM & Coherency Architectures\nARM Neoverse platforms\nAMBA AXI/AHB/APB\nARM CHI / CHI-E\nCMN (Coherent Mesh Network)\nCCIX\nCache Coherency Verification\nMulti-core CPU subsystem verification\nAI/HPC & Advanced SoC Technologies\nAI/ML Accelerator Verification\nNPU/GPU Verification\nNetwork-on-Chip (NoC)\nHigh-Performance Computing (HPC) SoCs\nData Center / Cloud Infrastructure SoCs\nRAS (Reliability, Availability, Serviceability)\nSecurity and TrustZone Verification\nPower Management & Low-Power Verification (UPF/CPF)\nPreferred Skills\nFormal Verification exposure.\nEmulation/FPGA prototyping experience.\nExperience with Synopsys VIP, Cadence VIP, or Siemens VIP.\nKnowledge of performance modeling and system-level verification.\nExperience with Verdi, DVE, SimVision, VCS, Xcelium, or Questa.\nOther Requirements","description_format":"text","description_chars":2530,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-23T11:53:27Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring 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