{"id":3968686,"url":"https://alion.io/job/hcltech-senior-design-lead-36","title":"Senior Design Lead","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Belgium"],"countries":["BE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Synplify Pro","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-11-09T15:11:25Z","employer_posted_date":"2026-11-09","last_verified_at":"2026-11-09T21:25:09Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nDigital Validation: 8 to 10 years’ experience in FPGA design and validation\nProfile\nExperience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation\nUnderstands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team.\nProven experience in digital design concepts and code development in VHDL/Verilog/system Verilog.\nExperience in adapting ASIC RTL code and replace blocks required to be able to fit it in an FPGA\nGood understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops.\nProven experience with synplify synthesis tool, Vivado place and route tool, Xilinx FPGAs\nExperience in writing C based tests for the FPGA testing.\nExperience in Python based code development.\nExperience in debug tools associated with FPGA debug.\nStrong experience in electronics fundamentals and debug.\nAbility to perform Device debug / Board debug and identify root cause, within an electrical validation environment.\nNeed to be thorough at bench level validation Oscilloscope and digital analyzers.\nFamiliar with revision control tools (SVN, run compute jobs)\nKey Responsibilities\nDigital Validation: 8 to 10 years’ experience in FPGA design and validation\nProfile\nExperience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation\nUnderstands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team.\nProven experience in digital design concepts and code development in VHDL/Verilog/system Verilog.\nExperience in adapting ASIC RTL code and replace blocks required to be able to fit it in an FPGA\nGood understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops.\nProven experience with synplify synthesis tool, Vivado place and route tool, Xilinx FPGAs\nExperience in writing C based tests for the FPGA testing.\nExperience in Python based code development.\nExperience in debug tools associated with FPGA debug.\nStrong experience in electronics fundamentals and debug.\nAbility to perform Device debug / Board debug and identify root cause, within an electrical validation environment.\nNeed to be thorough at bench level validation Oscilloscope and digital analyzers.\nFamiliar with revision control tools (SVN, run compute jobs)\nSkill Requirements\nOther Requirements","description_format":"text","description_chars":2622,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","Managed IT Services (MSP)","Systems Integrators","Engineering Services"],"lifecycle":[{"event":"open","at":"2026-11-09T15:11:25Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":27,"reasons":["conf:6","win:early","comp:brand"],"computed_at":"2026-11-10T03:35:41Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-design-lead-36","json_url":"https://alion.io/job/hcltech-senior-design-lead-36.json","meta":{"generated_at":"2026-11-10T03:35:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8397,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-11T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-design-lead-36"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-design-lead-36"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-design-lead-36"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-design-lead-36\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-design-lead-36"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3968686}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3968686},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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