{"id":3184030,"url":"https://alion.io/job/hcltech-senior-design-lead-design-validation-3","title":"Senior Design Lead - Design Validation","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-23T22:39:31Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-24T17:33:32Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nExperience 5 to 10 years.\nDefine ASIC/SoC verification strategy\nFull chip testplan development\nFull chip TB Architecture definition\nUVM based testbench development\nSV functional coverage, Assertions coding\nC based TB development\nTest case development, coding, execution, bug analysis\nGate Level Simulation\nRegressions, coverage analysis\nparticipate in verification closure.\nKey Responsibilities\nGood understanding of ASIC/SoC life cycle\nHas participated in multiple ASIC/SoC verification till tape out stage\nExperience writing ASIC/SoC test plans\nExperience in ASIC/SoC Testbench definition\nExperience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM).\"\nExpertise & hands-on experience in OVM/UVM methodologies using SV\nExperience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\"\nExperience in developing TB components for SOC with C, SV\nExperience in developing TB components, including functional coverage implementation and assertion coding\nExperience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\nDebug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\nExperience in SOC C based tests coding & debugging\"\nSkill Requirements\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nEDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).\nOther Requirements\nProtocols:\nDeep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).\"\nScripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for 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