Senior Design Lead - DFT
Confirmed on the employer's own hiring board on Oct 14, 2026. First seen by Alion on Oct 14, 2026.
Job Summary
B.Tech/ M.Tech with 4 to 8 years of experience exclusively in DFT.
Sub-system level: Hands-on experience to do scan insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Sub-system level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Good to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc.
DFX and DFD feature insertion and verification at SS level. SOC level verification for the same.
QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc.
Capable of doing SOC level verification, Pattern sim and delivery.
Should be able to handle cluster team of 2-3 members.
Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Good at Communication. Compatible of working Remotely / Hybrid method with multiple sites.
Key Responsibilities
1. Own Dft Planning, Execution, And Validation For Multiple Projects.
2. Ensure Delivery Of High-Quality Dft Features Within Schedule And Constraints.
3. Review Test Coverage Metrics And Optimize Atpg Patterns.
4. Resolve Complex Issues Across Synthesis, Timing, And Verification Phases.
Skill Requirements
1. -Extensive Knowledge Of Dft Tools And Techniques, Including Test Compression.
2. -Strong Analytical Skills For Diagnosing And Resolving Complex Design Issues.
3. -Experience In Multi-Project Planning And Execution.
4. -Ability To Influence Cross-Functional Teams And Stakeholders.
Other Requirements
1. Optional But Valuable Certifications: Certified Usability Analyst (Cua), Ux Design Professional Certificate, Or Equivalent Design Certifications.