{"id":1515247,"url":"https://alion.io/job/hcltech-senior-designer-design-validation","title":"Senior Designer - Design Validation","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-30T09:21:50Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-02T21:12:52Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nDefine ASIC/SoC verification strategy\nFull chip testplan development\nFull chip TB Architecture definition\nUVM based testbench development\nC based TB development\nSV functional coverage, Assertions coding\nTest case development, coding, execution, bug analysis\nGate Level Simulation\nRegressions, coverage analysis\nKey Responsibilities\nGood understanding of ASIC/SoC life cycle\nExperience writing ASIC/SoC testplans\n\"Experience in writing verification strategy document\n\"\n\"1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\n\"1. Experience in developing TB components for SOC with C, SV\n\"\n\"1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\"\n\"1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experince in SOC C based tests coding & debugging\"\n\"Experience in Gate level simulation & netlist debugging\n\"\n\"Exeprince in regression failure analayiss\nFunctioncal and Code Coverage closure\"\nSkill Requirements\nLanguages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nEDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).\nProtocols: Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe).\nScripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.\nOther Requirements\nBachelor's or Master's degree in Electronics & Communication Engineering (ECE),\nElectrical Engineering (EE), VLSI Design, or a closely related field","description_format":"text","description_chars":2296,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-09-30T09:21:50Z"}],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":1,"expected_fill_days":23,"reasons":["conf:12","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-designer-design-validation","json_url":"https://alion.io/job/hcltech-senior-designer-design-validation.json","meta":{"generated_at":"2026-10-03T04:09:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4263,"day_limit":5000,"remaining_today":737,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}