{"id":4207235,"url":"https://alion.io/job/hcltech-senior-developer-silicon-platform-validation-python","title":"Senior Developer - Silicon Platform Validation, Python","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Backend","role_family":"Backend","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-12T23:56:07Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T23:56:07Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nASIC and SoC verification roles require 5 to 7 years of relevant experience. The profile emphasizes verification ownership from testbench architecture through tapeout and closure.\nCandidates should develop reusable SystemVerilog and UVM testbenches, test plans, constrained-random tests, functional coverage, assertions, and regression analysis.\nResponsibilities include debugging simulations and netlists, analyzing waveforms and coverage gaps, supporting gate-level simulation, and performing verification closure.\nRequired qualifications include a relevant engineering degree, proficiency in Verilog and SystemVerilog, digital logic and bus protocol knowledge, EDA tool familiarity, and Linux scripting skills.\nKey Responsibilities\nGood understanding of ASIC/SoC life cycle\nHas participated in multiple ASIC/SoC verification till tapeout stage\nFull chip TB Architecture definitionExperience writing ASIC/SoC testplans\nUVM based testbench development\n1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans\nSkill Requirements\nC based TB development\n1. Experience in developing TB components for SOC with C, SV\nTest case development, coding, execution, bug analysis\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\nGate Level Simulation\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis\nFunctional and Code Coverage closure\nparticipate in verification closure\nExperience in Perl/Shell scripting\nEducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field\nCore Technical Skills\nLanguages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nEDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).\nProtocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).\"\nScripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation\nOther Requirements","description_format":"text","description_chars":3088,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","Managed IT Services (MSP)","Systems Integrators","Engineering Services"],"lifecycle":[{"event":"open","at":"2026-11-12T23:56:07Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":14,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-11-13T02:19:11Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-developer-silicon-platform-validation-python","json_url":"https://alion.io/job/hcltech-senior-developer-silicon-platform-validation-python.json","meta":{"generated_at":"2026-11-13T02:19:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4894,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-developer-silicon-platform-validation-python"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-developer-silicon-platform-validation-python"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-developer-silicon-platform-validation-python"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-developer-silicon-platform-validation-python\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-developer-silicon-platform-validation-python"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4207235}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4207235},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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