{"id":3341933,"url":"https://alion.io/job/hcltech-senior-group-technical-architect-44","title":"Senior Group Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-27T15:50:01Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-11-03T03:53:26Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Summary\nThe Silicon Design Verification Manager is responsible for leading pre-silicon verification of complex IP, subsystem, and SoC designs, ensuring functional correctness, coverage closure, schedule adherence, and strong customer alignment. The role combines technical depth, customer engagement, team leadership, and delivery governance across large-scale SoC programs.\nKey Responsibilities\nProgram & Delivery Ownership\nOwn end-to-end DV delivery for IP / Subsystem / SoC-level verification programs\nDrive verification planning, execution, coverage closure, and sign-off aligned to customer milestones\nEnsure monthly and sprint-wise planning, risk identification, dependency tracking, and mitigation\nAccountable for schedule, quality, and billing health, preventing leakage and delivery surprises\nTechnical Leadership\nDemonstrate strong understanding of SoC architecture, block boundaries, and ownership split (HCL vs customer)\nReview and guide DV architectures, testbench strategies, reuse, regressions, and coverage metrics\nProvide technical oversight for SV/UVM, assertions, formal verification, emulation, and regression flows\nLead debug discussions with RTL, architecture, and post-silicon teams\nCustomer Engagement\nAct as primary technical interface for DV topics with customer architects and verification leads\nDrive clear alignment on scope, estimates, deliverables, and milestones\nProactively handle customer escalations, communication, and expectation management\nLead MBRs / QBRs, ensuring no surprises through strong internal preparedness\nTeam & Capability Management\nAssess and maintain clear visibility into engineer skill levels, expertise, and readiness\nDefine effective team structures aligned to program complexity and timelines\nMentor DV leads and engineers; drive skill development and succession planning\nPartner with CUH / staffing teams for fulfillment, backfills, and risk mitigation\nGovernance & Reporting\nOwn MBR metrics, status reports, risk registers, and action tracking\nEnforce review cadence on deliverables, regressions, and quality metrics\nEnsure compliance to customer and organizational DV processes\nValue Creation & Future Readiness\nDrive value-add initiatives: productivity improvements, automation, and quality acceleration\nChampion GenAI and tool adoption where applicable in verification flows\nPlan buffers and capability ramp-ups for future SoC programs and technology nodes\nSkill Requirements\n15+ years in Silicon Design Verification, with experience leading large SoC programs\nStrong hands-on or review-level expertise in SystemVerilog, UVM, assertions, coverage, and debug\nSolid understanding of CPU/GPU, interconnects, memory subsystems, high-speed interfaces\nProven experience in customer-facing roles, escalations, and program leadership\nStrong people leadership, planning, and cross-functional collaboration skills\nOther Requirements\nPredictable delivery with zero billing leakage\nStrong customer confidence and fewer escalations\nHigh team utilization, skill maturity, and retention\nTangible value creation beyond baseline delivery\nBachelor’s/Master’s in Electrical/Electronics/Computer Engineering or related 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