{"id":2633015,"url":"https://alion.io/job/hcltech-senior-group-technical-architect-5","title":"Senior Group Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Python","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-10-15T16:44:42Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-15T21:22:16Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nCandidates with minimum 15 years' experience is mandatory\nDefine ASIC/SoC verification strategy:\nGood understanding of ASIC/SoC life cycle\nFull chip test plan development:\nHas participated in multiple ASIC/SoC verification till tape-out stage\nFull chip TB Architecture definition\nExperience writing ASIC/SoC test plans\nUVM based testbench development\n1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM).\"\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\nC based TB development\n1. Experience in developing TB components for SOC with C, SV\nTest case development, coding, execution, bug analysis\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\nGate Level Simulation\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis, Functional and Code Coverage closure\nOwn and execute verification closure\nExperience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.\nExperience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.\nExperience in Document test plans, micro-architecture specifications, and verification results for team reviews\nKey Responsibilities\nExperience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products\nEnd-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off. You will architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success\nEngineering Execution\nDevelop complex verification components, including bus functional models (BFMs), monitors, predictors, and highly parameterized scoreboards.\nOversee and resolve deep technical issues in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, and formal verification.\nDirect the deployment of advanced verification techniques such as Formal Verification, Hardware Emulation (e.g., Palladium, Zebu), and Power-Aware (UPF/CPF) simulations.\nManagement & Strategy\nAct as the primary technical point of contact, interfacing with System Architects, Backend/Physical Design teams, and Post-Silicon Validation teams.\nProvide technical mentorship, code reviews, and career guidance to junior and mid-level design and verification engineers.\nEstablish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.\nSkill Requirements\nCore Technical Skills\nProven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.\nExpert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nProcessor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.\"\nTools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.\nProtocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).\"\nScripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.\nSoft Skills\nStrategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.\nInfluence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.\nOther Requirements\nEducationDegree:\nBachelor's or Master's degree in Electronics & Communication Engineering (ECE),\nElectrical Engineering (EE), VLSI Design, or a closely related field\"","description_format":"text","description_chars":4745,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT 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