{"id":2816931,"url":"https://alion.io/job/hcltech-senior-solution-architect-18","title":"Senior Solution Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Solutions","role_family":"Solutions","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":61000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":36},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Pegasus","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-10-18T14:05:38Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-21T10:51:54Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nA Physical Design Chip Lead (or Full-Chip Physical Design Lead) is a highly experienced VLSI professional who owns the end-to-end digital implementation and tape-out delivery of an entire Integrated Circuit (IC) or System-on-Chip (SoC). This role requires a balance of expert-level technical execution (RTL-to-GDSII) and project leadership to guide execution teams, manage schedule risks, and bridge the gap between architecture and silicon manufacturing.\nKey Responsibilities\nJob summary: We are seeking a highly technical and execution-driven Physical Design Chip Lead to spearhead the structural design, implementation, and physical sign-off of our next-generation, high-performance SoCs. In this role, you will own the entire full-chip physical design lifecycle-from early architectural feasibility, floorplanning, and synthesis through final GDSII tape-out. You will lead a team of talented physical design engineers, establish sign-off methodologies, and collaborate directly with architects, front-end designers, and foundry partners to deliver best-in-class Power, Performance, and Area (PPA) on advanced process nodes.\nSkill Requirements\nDrive the execution of the entire hierarchical RTL-to-GDSII physical design flow, including synthesis, floorplanning, place & route (PnR), clock tree synthesis (CTS), timing closure, and physical verification.\n· Define the physical implementation strategy, schedule milestones, and allocate resources across block-level and full-chip integration tasks. Identify and mitigate technical or schedule risks early.\n· Partner with SoC architects to conduct early feasibility studies. Drive top-level floorplanning, package/bump placement, macro integration, and full-chip Power Distribution Network (PDN) definitions.\n· Establish strict sign-off criteria and methodologies for the project across all domains: Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), Low Power Compliance (VCLP/UPF), and Physical Verification (DRC/LVS/ERC).\n· Act as the primary engineering bridge between RTL Front-End, Design Verification (DV), DFT, Packaging, Signal/Power Integrity, and external Silicon Foundries.\n· Lead the final closure push for the full-chip database, auditing waivers, reviewing engineering change orders (ECOs), and authorizing final tape-out release.\n· Guide, mentor, and perform technical reviews for junior and mid-level physical design engineers to elevate the team's technical capabilities\nOther Requirements\n· with a proven track record of leading or co-leading complex full-chip SoC tape-outs.\n· Core flow mastery: Synopsys (Fusion Compiler, IC Compiler II, PrimeTime, StarRC, VC LP) or Cadence (Innovus, Tempus, Quantus, Pegasus, Voltus)\n· Advanced nodes: Extensive tape-out experience on sub-7nm FinFET or GAA process nodes (e.g., TSMC/Intel/Samsung N5, N3, N2) handling tight design rules and complex multi-patterning layouts.\n· advanced clock-tree architectures, hierarchical UPF low-power designs, and chip-package co-design.\n· Proficient in TCL/python/Shell","description_format":"text","description_chars":3042,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-18T14:05:38Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":2,"expected_fill_days":30,"reasons":["conf:1","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-solution-architect-18","json_url":"https://alion.io/job/hcltech-senior-solution-architect-18.json","meta":{"generated_at":"2026-10-21T12:31:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17687,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-solution-architect-18"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-solution-architect-18"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-solution-architect-18"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-solution-architect-18\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-solution-architect-18"}]}