{"id":2816932,"url":"https://alion.io/job/hcltech-senior-solution-architect-19","title":"Senior Solution Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Solutions","role_family":"Solutions","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":37000,"max_usd":64000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":36},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-10-18T14:05:38Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-23T11:59:33Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Summary\nWe are seeking a highly experienced Clocking/Constraints/STA Lead to join our Physical Design team. In this critical leadership role, you will not only be responsible for your own technical expertise but also for guiding and mentoring a team of engineers to achieve exceptional timing closure for our IC designs. Full Chip Static Timing Analysis (STA) Engineer verifies that an entire System-on-Chip (SoC) meets all speed and performance requirements across every operational condition without running full logical simulations\nLocation: Bangalore/Hyderabad/Noida/Chennai\nKey Responsibilities\nLead the development and implementation of comprehensive clocking strategies for high-performance ICs.\n· Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis.\n· Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks.\n· Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control.\n· Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan.\n· Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges.\n· Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA.\n· latest advancements in clocking methodologies, timing analysis tools, and industry best practices.\n· Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency.\n· Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team.\nSkill Requirements\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field (preferred) or Bachelor's degree with extensive experience.\n· Minimum of 15+ years of experience in clocking, constraints, and STA for digital IC design.\n· Understanding of On-Chip Variation (OCV/POCV), clock tree architecture, parasitic extraction (SPEF), and gate-level netlists\n· Proven leadership experience in managing and motivating a team of engineers.\n· In-depth knowledge of digital design principles, timing analysis methodologies, and clock tree synthesis techniques.\n· Expert-level proficiency in industry-standard STA tools (e.g., Synopsys PrimeTime, Mentor Questa Timing Analyzer).\n· Strong understanding of clock domain crossing (CDC) verification concepts and methodologies.\n· Excellent communication, collaboration, and interpersonal skills.\n· Ability to think strategically, solve complex timing closure problems, and make sound technical decisions.\n· Proven ability to manage multiple projects and meet aggressive deadlines in a fast-paced environment.\nOther Requirements\nSkills:\n· Clocking\n· Timing constraint development (Full chip Must)\n· STA tools: Innovus, Synopsys PrimeTime, Mentor Questa Timing Analyze\n· Understanding of On-Chip Variation (OCV/POCV), clock tree architecture, parasitic extraction (SPEF), and gate-level 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