{"id":2816933,"url":"https://alion.io/job/hcltech-senior-solution-architect-20","title":"Senior Solution Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Solutions","role_family":"Solutions","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":62000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":36},"experience_years_min":18,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-10-18T14:05:38Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-20T23:46:24Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nThe DFT Architect will be responsible for defining, driving, and governing the complete Design-for-Test (DFT) strategy for complex SoCs delivered under a turnkey/outcome-based engagement model. The role owns DFT architecture from feasibility through silicon bring-up, ensuring testability, manufacturability, quality, coverage, schedule adherence, and customer acceptance.\nThe architect serves as the technical authority for all DFT-related decisions and works closely with SoC Architects, RTL, Integration, Verification, Physical Design, STA, Packaging, ATE, Product Engineering, and Foundry teams\nDFT Architecture & Strategy\nDefine SoC-level DFT architecture and test strategy during feasibility and architecture phases.\nCreate DFT specifications, test architecture documents, and implementation guidelines.\nEstablish hierarchical DFT methodology across IP, Subsystems, and SoC.\nDrive testability requirements into architecture and micro-architecture reviews.\nDefine scan partitioning, test access mechanisms, compression strategy, and test modes.\nDefine manufacturing test, diagnostics, and yield enhancement strategy.\nDFT Planning & Technical Leadership\nOwn DFT estimation, planning, risks, schedules, and milestone tracking.\nReview third-party IP test readiness and integration requirements.\nLead DFT design reviews and sign-off reviews.\nDrive customer discussions and provide technical guidance.\nMentor DFT engineers, leads, and subsystem owners.\nDFT Implementation Ownership\nDrive implementation of:\nScan Insertion\nEDT/Test Compression\nMBIST\nLBIST\nBoundary Scan (IEEE 1149.1/1149.6)\nIJTAG/IEEE 1687\nOCC (On-Chip Clock Controller)\nTest Point Insertion\nSSN (Streaming Scan Network)\nHigh-Speed Interface Testing\nSecurity-aware DFT features\nResolve complex DRC and testability issues.\nEnsure DFT compliance across large multi-power and multi-clock SoCs.\nKey Responsibilities\nATPG & Coverage Closure\nOwn ATPG methodology and sign-off.\nDrive stuck-at, transition, path-delay, cell-aware, and bridge fault coverage closure.\nAnalyze coverage loss and implement improvement strategies.\nDefine diagnostic pattern generation methodology.\nReview test quality metrics and coverage goals.\nDFT Verification & Sign-off\nDefine DFT verification strategy.\nReview:\nDFT RTL verification\nGate-Level Simulations\nTest Mode Verification\nTest Timing Verification\nFormal Equivalence\nDFT CDC requirements\nEnsure sign-off quality prior to tape-out.\nPhysical Design & STA Collaboration\nWork closely with PD teams on:\nScan chain optimization\nOCC implementation\nTest clock architecture\nTest-mode timing closure\nCongestion and routing impacts\nEnsure DFT-aware floorplanning and implementation.\nTest Program & Silicon Readiness\nPartner with Product Engineering and ATE teams.\nDefine pattern handoff strategy.\nSupport tester pattern generation and debug.\nReview production test flows.\nLead silicon bring-up DFT debug.\nDrive yield improvement initiatives and diagnosis activities.\nTurnkey Program Responsibilities\nParticipate in:\nFeasibility Review\nProject Kickoff\nDesign Kickoff\nArchitecture Reviews\nMilestone Sign-offs\nChange Control Board Reviews\nOwn DFT delivery quality, schedule, and customer commitments.\nSupport program risk assessment and mitigation planning.\nContribute to project execution methodology and best practices. [Turnkey FP...amework_v1 | Word], [BI-WEEKLY_...G2026_v3.1 | PowerPoint]\nSkill Requirements\nMandatory Technical Skills Required :- 18-25 years of DFT experience.\nMultiple successful SoC tape-outs.\nExpertise in:\nScan\nMBIST\nATPG\nEDT/Test Compression\nLBIST\nBoundary Scan\nOCC\nDFX methodologies\nStrong understanding of:\nRTL Design\nSoC Integration\nPhysical Design\nSTA\nLow Power Architectures\nMulti-clock and Multi-power SoCs\nExperience with advanced nodes (16nm and below preferred).\nEDA Tools\nSynopsys DFT Compiler\nTessent Suite\nModus\nTetraMAX/TestMAX\nATPG Tools\nSpyglass DFT\nPrimeTime\nGenus/Design Compiler\nInnovus/Fusion Compiler\nVerdi\nOther Requirements\nDesirable\nAutomotive (ISO 26262) DFT methodologies.\nSafety and diagnostic coverage analysis.\nAdvanced packaging/chiplet test strategies.\nSilicon debug and yield ramp expertise.\nAnalog/Mixed Signal DFT experience (PLL, DDR, MIPI, ADC/DAC, SerDes, USB). [HCLTech_se...s_detailed | PowerPoint], [Capability Deck_v1 | PowerPoint], [HCLTech Te...March 2026 | PowerPoint]\nLeadership Expectations\nTechnical owner for DFT workstream in a turnkey SoC program.\nLead teams of 10-50+ DFT engineers across geographies.\nInterface directly with customer architects and management.\nDrive technical decisions impacting schedule, quality, and manufacturability.\nEstablish reusable DFT methodology, automation, and best practices.\nMentor future DFT leads and architects.\nSuccess Metrics\nTest Coverage Achievement (>95% Stuck-at, >90% Transition as program targets).\nZero critical DFT escapes at tape-out.\nFirst-pass silicon success.\nDFT milestone adherence.\nYield ramp support effectiveness.\nCustomer satisfaction and technical acceptance.\nReuse and standardization across programs. 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