{"id":3092776,"url":"https://alion.io/job/hcltech-senior-solution-architect-28","title":"Senior Solution Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Solutions","role_family":"Solutions","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":57000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":37},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-22T15:20:16Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-28T02:46:04Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Summary\nLead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tape out.\nKey Responsibilities\nRTL Integration Ownership\nOwn top-level RTL integration of SoC:\nIntegrate multiple IPs, subsystems, and third-party blocks\nEnsure clean connectivity, hierarchy, and modular structure\nDeliver synthesis-ready, lint-clean, and CDC-clean RTL\nArchitecture Alignment\nWork closely with architecture teams to:\nTranslate SoC architecture into RTL structure\nEnsure correct implementation of:\nInterconnects (NoC / bus-based)\nAddress maps\nReset and clock architecture\nInterface & Connectivity Management\nDefine and validate:\nIP interfaces and protocols (AXI, AHB, APB, etc.)\nAddress decoding and interconnect connectivity\nResolve:\nInterface mismatches\nIntegration conflicts across teams\nClock, Reset & Power Integration\nKey Responsibilities\nDefine and integrate:\nClocking architecture (multiple clock domains)\nReset strategies (global/local resets)\nPower domains (UPF/CPF alignment)\nEnsure:\nClean CDC/RDC implementation\nProper low-power intent integration\nQuality & Signoff Readiness\nDrive RTL quality checks:\nLint (SpyGlass, Lint tools)\nCDC/RDC analysis\nBasic synthesis checks\nEnsure RTL is:\nDV-ready\nDFT-ready\nPD-friendly\nCollaboration Across Teams\nInterface with:\nIP/RTL design teams\nDV teams (for testbench integration support)\nDFT teams (for scan/test readiness)\nPD/STA teams (for implementation alignment)\nAct as central integration point across all domains\nDebug & Issue Resolution\nLead debug of:\nIntegration bugs\nBoot-up and reset sequence issues\nConnectivity and functional mismatches\nSupport system-level bring-up in simulation/emulation\nAutomation & Flow Development\nDevelop scripts/tools for:\nRTL stitching\nConnectivity checks\nBuild and regression flows\nImprove integration efficiency and repeatability\nSkill Requirements\nLeadership\nLead and mentor RTL integration engineers\nDrive integration schedules, milestones, and reviews\nAct as owner of top-level RTL quality and readiness\nRequired Skills & Expertise\nTechnical\nStrong expertise in:\nVerilog/SystemVerilog RTL design\nSoC integration and architecture\nDeep understanding of:\nBus protocols (AXI/AHB/APB)\nClock/reset domain design\nLow-power design (UPF/CPF basics)\nExperience with:\nLint, CDC/RDC tools\nSynthesis awareness\nExperience\n15-18+ years in RTL design/integration\nProven experience in:\nChip-level RTL integration ownership\nMultiple SoC tapeouts\nOther Requirements\nTools\nLint: SpyGlass / Questa Lint\nCDC: SpyGlass CDC / Questa CDC\nSynthesis: Design Compiler / Genus (basic awareness)\nVersion control: Git/Perforce\nSoft Skills\nStrong system-level thinking\nExcellent coordination across large teams\nProblem-solving and debugging mindset\nGood to Have\nExperience in:\nNoC-based SoC architectures\nEmulation/FPGA bring-up\nFirmware/boot flow understanding\nScripting:\nPython / TCL / Perl\nSuccess Metrics\nClean, integration-ready RTL (lint/CDC clean)\nSmooth handoff to DV, DFT, and PD teams\nMinimal integration bugs at system level\nPredictable integration schedules\nFirst-pass success in SoC bring-up","description_format":"text","description_chars":3263,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-22T15:20:16Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring 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