{"id":3150293,"url":"https://alion.io/job/hcltech-senior-solution-architect-32","title":"Senior Solution Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Solutions","role_family":"Solutions","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":32000,"max_usd":56000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":37},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Verdi","optional":true}],"status":"live","first_seen_at":"2026-10-23T11:53:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-27T15:50:01Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Summary\nRole Overview\nLead and own chip-level verification strategy and execution for complex SoCs, ensuring functional correctness, coverage closure, and high-quality tapeouts. This role requires deep expertise in system-level verification, integration challenges, and leadership across multiple IP/block teams.\n������Key Responsibilities\n������Verification Ownership\nOwn end-to-end chip-level DV from planning to signoff\nDefine and drive verification strategy, including reuse of block-level environments\nEnsure functional correctness of integrated SoC across all subsystems\n������Testbench & Methodology\nArchitect and develop scalable chip-level testbenches (typically UVM-based)\nDrive reuse and integration of block/IP-level verification environments\nEnsure best practices in:\nStimulus generation\nScoreboarding\nAssertions (SVA)\nCoverage models\n������Integration & Debug\nHandle complex SoC integration issues:\nInterface mismatches\nProtocol violations\nReset/boot sequence issues\nLead debug of system-level failures and root cause analysis\nWork closely with RTL, architecture, and firmware teams\n������Coverage Closure\nDefine and track:\nFunctional coverage\nCode coverage (line/toggle/branch/FSM)\nDrive closure to meet tapeout criteria\nIdentify and close coverage holes and corner cases\nKey Responsibilities\n������Cross-Functional Collaboration\nCollaborate with:\nRTL design teams\nFirmware/software teams (for boot/use-case validation)\nEmulation/FPGA teams\nPost-silicon validation teams\nEnsure alignment between pre-silicon and post-silicon validation plans\n������Platform & Performance\nEnable verification on:\nSimulation platforms\nEmulation (Palladium/Zebu)\nFPGA prototyping (optional)\nOptimize regression performance and turnaround time\n������Leadership\nLead and mentor a team of DV engineers\nDrive verification planning, reviews, and signoff\nDefine quality metrics, schedules, and execution tracking\nAct as single point of ownership for DV signoff\n������Required Skills & Expertise\n������Technical\nStrong expertise in:\nSystemVerilog & UVM methodology\nAssertions (SVA)\nFunctional coverage\nExperience in:\nSoC-level verification\nComplex protocols (AXI, PCIe, DDR, etc.)\nSolid understanding of:\nComputer architecture / SoC architecture\nLow-power verification (UPF/CPF basics)\n������Experience\n12-18+ years in Design Verification\nProven track record of:\nLeading chip-level DV\nMultiple successful SoC tapeouts\nSkill Requirements\n������Tools & Platforms\nSimulators: VCS, Xcelium, Questa\nEmulation: Palladium, Zebu (good to have)\nDebug tools: Verdi, SimVision\n������Soft Skills\nStrong debugging and analytical thinking\nAbility to lead large, cross-functional teams\nClear communication with stakeholders and customers\n������Good to Have\nExperience with:\nPortable Stimulus (PSS)\nFormal verification exposure\nFirmware-driven verification\nScripting:\nPython / Perl / TCL for automation\nOther Requirements\n������Success Metrics\nFunctional + code coverage closure as per targets\nHigh bug detection efficiency pre-silicon\nMinimal escapes to silicon\nRegression stability and turnaround time\nFirst-pass silicon success (functional perspective)","description_format":"text","description_chars":3131,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-23T11:53:27Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring 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