{"id":2929477,"url":"https://alion.io/job/hcltech-senior-technical-architect-53","title":"Senior Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Backend","role_family":"Backend","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["São Paulo, Brazil"],"countries":["BR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":75000,"max_usd":161000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":2286},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"CI/CD","optional":true}],"status":"live","first_seen_at":"2026-10-20T14:17:11Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-20T18:59:33Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nPhysical Design CAD Support Engineer to support and optimize Physical Design EDA tools and flows for advanced silicon programs. Responsible for troubleshooting complex tool and methodology issues, providing Tier 2/3 support, and driving improvements in flow stability, automation, and design productivity. Strong expertise in Synopsys Fusion Compiler, PrimeTime, and Cadence Innovus\nKey Responsibilities\nPhysical Design Tool & Flow Support\nProvide Tier 2 and Tier 3 support for Physical Design engineers across backend implementation and signoff flows.\nSupport, maintain, and troubleshoot Physical Design methodologies, CAD infrastructure, and EDA tool environments.\nInvestigate and resolve complex tool, flow, runtime, and design convergence issues impacting project schedules.\nDiagnose and debug failures related to floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff.\nWork directly with design teams to understand issues, reproduce failures, and drive resolution.\nEDA Tool Expertise\nAct as a subject matter expert for Synopsys and Cadence Physical Design tools.\nProvide support for:\nSynopsys Fusion Compiler (FC)\nSynopsys PrimeTime (PT)\nCadence Innovus\nSiemens Calibre (Physical Verification & Signoff)\nAnalyze tool behavior, log files, databases, and performance bottlenecks to determine root causes.\nEngage with EDA vendors on tool defects, enhancement requests, and patch validations.\nDebugging, Root Cause Analysis & Issue Resolution\nPerform detailed debugging of CAD flow failures and design-tool issues.\nConduct root cause analysis for recurring flow and methodology problems.\nDrive corrective and preventive actions to improve overall flow robustness.\nDevelop workarounds and permanent fixes for tool and methodology issues.\nCreate troubleshooting guides and knowledge-base documentation for common issues.\nCAD Flow Development & Automation\nDevelop and enhance Physical Design CAD flows and methodologies.\nCreate automation solutions using TCL, Python, Shell scripting, and workflow automation frameworks.\nImprove flow reliability, scalability, and runtime efficiency through automation and continuous improvements.\nSupport tool deployment, release qualification, and regression validation activities.\nCross-functional Collaboration\nPartner with Physical Design, STA, DFT, CAD Methodology, and Silicon Engineering teams.\nSupport project execution by ensuring stable and efficient implementation flows.\nMentor junior engineers on debugging methodologies and CAD best practices.\nContribute to strategic improvements in CAD infrastructure and design methodologies.\nSkill Requirements\nKey Skills\nFusion Compiler | PrimeTime | Innovus | Siemens Calibre | Physical Design | CAD Flow Support | EDA Tools | Root Cause Analysis | Flow Debugging | Tier 2 Support | Tier 3 Support | Physical Verification | TCL | Python | Linux | Semiconductor CAD Methodology\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.\n7+ years of experience in Physical Design, CAD Engineering, or EDA Tool Support.\nStrong hands-on expertise with: Synopsys Fusion Compiler, Synopsys PrimeTime, Cadence Innovus, Siemens Calibre.\nDeep understanding of Physical Design implementation flows and timing closure methodologies.\nStrong TCL, Python, and Linux scripting skills.\nProven experience troubleshooting complex EDA tool and flow issues.\nExperience providing Tier 2/Tier 3 customer or engineering support.\nExcellent analytical, debugging, communication, and problem-solving skills.\nPreferred Qualifications\nExperience with advanced-node designs (7nm, 5nm, 3nm, or below).\nKnowledge of low-power methodologies, UPF, EM/IR, and physical verification flows.\nExperience supporting enterprise CAD environments and distributed compute infrastructures.\nFamiliarity with CI/CD, regression frameworks, and automated flow validation.\nExperience working directly with Synopsys and Cadence support organizations.\nOther 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