{"id":3414857,"url":"https://alion.io/job/hcltech-senior-technical-architect-86","title":"Senior Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":99000,"max_usd":167000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":17},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Python","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-10-28T18:57:08Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-11-01T14:56:34Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Summary\nCandidates with 8 to 14 years experience is mandatory Define ASIC/SoC verification strategy: Good understanding of ASIC/SoC life cycle Full chip testplan development: Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\" 1. Ethernet verfication 2.PCIe 3.UCIe SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB components for SOC with C, SV Test case development, coding, execution, bug analysis 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experience in SOC C based tests coding & debugging Gate Level Simulation Experience in Gate level simulation & netlist debugging Regressions, coverage analysis Experience in regression failure analysis, Functional and Code Coverage closure Own and execute verification closure Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files. Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently. Experience in Document test plans, micro-architecture specifications, and verification results for team reviews EducationDegree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field\" Core Technical Skills Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs. Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology). Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.\" Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms. Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).\" Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking. Soft Skills Strategic Thinking: Ability to foresee technical risks weeks or months in advance and p\nKey Responsibilities\n1. To design and architect large-scale solutions, ensuring scalability, performance, and security.\n2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.\n3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.\n4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.\nSkill Requirements\nnull\nOther Requirements\nnull","description_format":"text","description_chars":3841,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Professional Services","Science & Engineering","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-28T18:57:08Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":3,"expected_fill_days":31,"reasons":["conf:1","wave","velocity","win:early","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-architect-86","json_url":"https://alion.io/job/hcltech-senior-technical-architect-86.json","meta":{"generated_at":"2026-11-01T17:47:48Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27276,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-architect-86"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-architect-86"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-architect-86"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-architect-86\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-architect-86"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3414857}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3414857},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}