{"id":3448432,"url":"https://alion.io/job/hcltech-senior-technical-architect-allegro-pcb","title":"Senior Technical Architect - Allegro PCB","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":58000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false}],"status":"live","first_seen_at":"2026-10-29T09:41:10Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-01T10:07:04Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Summary\nOwn end-to-end PCB layout for complex, high-density designs used in data center server boardsPerform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigationDevelop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form factorsCollaborate with electrical engineers to review schematics and provide layout-driven feedback on component placement, power distribution network design, and signal routing strategiesPartner with mechanical engineers to resolve physical constraints including board outline, connector placement, thermal management, and stack-up definitionDrive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure layouts meet yield and reliability targetsMaintain and improve PCB design standards, layer stack-up libraries, and footprint libraries to support scalable development across multiple hardware programsSupport by providing layout documentation, net tracing support, and design revision analysis for prototype and production boards\nKey Responsibilities\nSkill Requirements 1. Advanced Proficiency In Allegro Pcb For Pcb Layout And Design.\n2. Strong Knowledge Of Cad Software For 2D And 3D Design Applications.\n3. 10-14 years of CAD experience, Cadence Allegro Layout tool 23.1 and above experience is mandatory4. Hands on experience in HDI micro via( Blind/Buried) technology 5.Intel or high complex SoC/Microprocessor/FPGA based PCB design experience preferred\n6. high complex SoC/Microprocessor/FPGA based PCB design experience preferred7.Ability to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen 5 or Gen 6, Power Delivery, Mixed Analog/Digital8.Deep knowledge of CES (Constraint Editor) and high -speed constraint driven designs, DFA/DFM/DFT knowledge to adhere to Quality PCB fabrication and assembly assurance9.Strong Communication And Presentation Abilities To Effectively Convey Design Concepts.SKILL section. 4 of 6.\nSkill Requirements\nSkill Requirements 1. Advanced Proficiency In Allegro Pcb For Pcb Layout And Design.\n2. Strong Knowledge Of Cad Software For 2D And 3D Design Applications.\n3. 10-14 years of CAD experience, Cadence Allegro Layout tool 23.1 and above experience is mandatory4. Hands on experience in HDI micro via( Blind/Buried) technology 5.Intel or high complex SoC/Microprocessor/FPGA based PCB design experience preferred\n6. high complex SoC/Microprocessor/FPGA based PCB design experience preferred7.Ability to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen 5 or Gen 6, Power Delivery, Mixed Analog/Digital8.Deep knowledge of CES (Constraint Editor) and high -speed constraint driven designs, DFA/DFM/DFT knowledge to adhere to Quality PCB fabrication and assembly assurance9.Strong Communication And Presentation Abilities To Effectively Convey Design Concepts.SKILL section. 4 of 6.\nOther Requirements","description_format":"text","description_chars":3092,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Professional Services","Science & Engineering","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-29T09:41:10Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":31,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-architect-allegro-pcb","json_url":"https://alion.io/job/hcltech-senior-technical-architect-allegro-pcb.json","meta":{"generated_at":"2026-11-01T11:41:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18151,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-architect-allegro-pcb"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-architect-allegro-pcb"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-architect-allegro-pcb"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-architect-allegro-pcb\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-architect-allegro-pcb"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3448432}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3448432},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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