{"id":2811989,"url":"https://alion.io/job/hcltech-senior-technical-architect-c-post-silicon-validation-python-2","title":"Senior Technical Architect - C, Post - silicon Validation, Python","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":153000,"max_usd":278000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":527},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"BERT","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-18T09:46:44Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-24T17:33:32Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Summary\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication;\nPresent a margin plot and a root-cause story to design and program teams\nKey Responsibilities\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\nPresent a margin plot and a root-cause story to design and program teams\nSkill Requirements\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\nPresent a margin plot and a root-cause story to design and program teams\nOther Requirements\nRequirements:\n10+ years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs\nHands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.\nLab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue\nWorking knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs\nAbility to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware\nScripting for lab automation and data analysis (Python preferred)\nClear written and verbal communication\nPresent a margin plot and a root-cause story to design and program teams","description_format":"text","description_chars":3303,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-18T09:46:44Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.895,"p_room":1,"age_days":6,"expected_fill_days":30,"reasons":["conf:12","velocity","win:early","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-architect-c-post-silicon-validation-python-2","json_url":"https://alion.io/job/hcltech-senior-technical-architect-c-post-silicon-validation-python-2.json","meta":{"generated_at":"2026-10-25T09:20:32Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13371,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-architect-c-post-silicon-validation-python-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-architect-c-post-silicon-validation-python-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-architect-c-post-silicon-validation-python-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-architect-c-post-silicon-validation-python-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-architect-c-post-silicon-validation-python-2"}]}