{"id":3448442,"url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-10","title":"Senior Technical Lead - Post Silicon Validation","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":65000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"ANSYS","optional":false},{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"Ansys HFSS","optional":true},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Sigrity","optional":true},{"name":"Synopsys IC Validator","optional":true}],"status":"live","first_seen_at":"2026-10-29T09:41:10Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-06T10:43:51Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Job Summary\nWe are looking for a Silicon Interposer Design Engineer to drive the physical design, layout, and technology development of silicon interposers used in next-generation 2.5D and 3D heterogeneous integration platforms. You will own the interposer design from architecture definition through tapeout, working at the intersection of semiconductor process technology, package integration, and system-level performance optimization.\nKey Responsibilities\nLead the physical design and layout of silicon interposers for multi-chiplet integration (compute, HBM, I/O, networking dies)\nDefine interposer architecture including die placement, bump map assignment, RDL routing strategy, TSV farm layout, and power/ground distribution\nDevelop and optimize RDL (Redistribution Layer) routing for high-density die-to-die interconnects, ensuring compliance with electrical, thermal, and mechanical constraints\nDesign TSV (Through-Silicon Via) arrays and transitions - including TSV placement, keep-out zones, stress-aware floorplanning, and landing pad optimization\nCollaborate with SI/PI engineers to meet signal integrity and power delivery targets across the interposer\nDefine and validate interposer stackup (metal layers, dielectric thickness, TSV dimensions) in coordination with foundry process capabilities\nPerform DRC/LVS verification and ensure design compliance with foundry design rules (TSMC CoWoS, UMC, GlobalFoundries, etc.)\nWork with EDA tool flows for interposer-specific design (custom routing, via pillar arrays, micro-bump pitch optimization)\nCo-optimize interposer design with package substrate and PCB teams for seamless chip-package-board integration\nSupport thermal-mechanical analysis by providing accurate layout data for warpage, stress, and reliability simulations\nInterface with foundry partners for technology selection, design rule clarification, and tapeout execution\nDrive DFM/DFT strategies to improve yield and testability of interposer-based products\nSupport silicon bring-up, debug, and failure analysis of interposer-related issues\nSkill Requirements\n5+ years of experience in silicon interposer design, advanced packaging physical design, or semiconductor back-end-of-line (BEOL) design\nStrong proficiency with physical design and layout tools:\nLayout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package Designer), Synopsys IC Compiler II, Siemens Calibre\nVerification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC)\nParasitic Extraction: StarRC, QRC, Calibre xRC\nDeep understanding of silicon interposer process technology:\nRDL metallization (Cu damascene, semi-additive process)\nTSV fabrication (via-first, via-middle, via-last)\nMicro-bump and C4 bump technology\nWafer thinning and backside processing\nExperience with high-density routing at fine pitch (< 1 µm L/S for RDL, < 10 µm TSV pitch)\nKnowledge of design-for-reliability (DFR): electromigration, stress migration, thermal cycling, and Cu pumping in TSVs\nFamiliarity with foundry PDKs and process design kits for interposer technologies\nScripting skills (Python, Tcl, SKILL) for design automation and custom DRC rule development\nOther Requirements\nTechnical Environment Domain Tools & Technologies Physical Design & Layout Cadence Virtuoso, APD, Allegro SiP, Synopsys IC Compiler II Verification (DRC/LVS) Parasitic Extraction EM/Electrical Analysis Thermo-Mechanical Scripting & Automation Foundry Platforms Interconnect Standards Cadence PVS, Siemens Calibre, IC Validator StarRC, QRC, Calibre xRC Ansys HFSS, Cadence Clarity, Sigrity Ansys Mechanical, Ansys Icepak, COMSOL Multiphysics Python, Tcl, Cadence SKILL, Perl TSMC CoWoS (S/R/L), UMC, GlobalFoundries, Samsung I-Cube UCIe, HBM3/3E PHY, PCIe Gen5/6, high-speed SerDes\nPreferred Qualifications\nDirect experience with TSMC CoWoS (CoWoS-S, CoWoS-R, CoWoS-L), Intel EMIB, or similar 2.5D interposer platforms\nExperience designing interposers for HBM integration (HBM2E/HBM3/HBM3E PHY-to-interposer routing)\nKnowledge of hybrid bonding and direct Cu-Cu interconnect technology for next-generation interposers\nFamiliarity with chiplet standards (UCIe, BoW) and their physical implementation on interposers\nExperience with organic interposer or glass-core interposer alternatives\nUnderstanding of thermo-mechanical simulation tools (Ansys Mechanical, COMSOL) for warpage and stress analysis\nExposure to photonics integration on silicon interposers (co-packaged optics)\nTrack record of successful tapeouts with major foundries\nPublications or patents in advanced packaging or interposer technology","description_format":"text","description_chars":4544,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Professional Services","Science & Engineering","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-29T09:41:10Z"}],"visa":[],"liveness":{"score":98,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.981,"p_room":1,"age_days":7,"expected_fill_days":26,"reasons":["conf:0","wave","velocity","win:early","comp:brand"],"computed_at":"2026-11-06T05:58:05Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-10","json_url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-10.json","meta":{"generated_at":"2026-11-06T11:21:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20639,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-07T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-10"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-10"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-10"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-lead-post-silicon-validation-10\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-10"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3448442}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3448442},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}