{"id":3387611,"url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-8","title":"Senior Technical Lead - Post Silicon Validation","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":66000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Ansys RedHawk","optional":false},{"name":"Ansys SIwave","optional":false},{"name":"Cadence Clarity 3D Solver","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"Cadence Spectre","optional":false},{"name":"Cadence Voltus","optional":false},{"name":"Keysight ADS","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"Mentor Xpedition","optional":true},{"name":"Perl","optional":true},{"name":"Synopsys IC Compiler II","optional":true}],"status":"live","first_seen_at":"2026-10-28T08:26:33Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-31T12:16:29Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Summary\nWe are seeking an experienced SI/PI Engineer to join our Advanced Silicon Packaging team. In this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces.\nKey Responsibilities\nPerform SI/PI analysis and design optimization for advanced silicon packages (CoWoS, EMIB, chiplet-based architectures, fan-out wafer-level packaging)\nDevelop and validate high-speed channel models for package interconnects including bumps, microbumps, TSVs, RDL layers, and silicon/organic interposers\nConduct full-wave electromagnetic (EM) simulations of package structures to characterize S-parameters, crosstalk, impedance, and insertion/return loss\nDesign and optimize Power Distribution Networks (PDN) - including decoupling strategy, IR drop analysis, and AC impedance profiling from die to board\nPerform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps)\nCollaborate with IC design, package substrate design, PCB layout, and thermal/mechanical teams to co-optimize package electrical performance\nDevelop and correlate simulation models with lab measurements (VNA, TDR, oscilloscope, power noise measurements)\nDefine SI/PI design guidelines and constraints for package substrate stackup, routing rules, and bump/via assignments\nSupport design-for-manufacturability (DFM) reviews with OSAT partners and substrate vendors\nInvestigate and resolve SI/PI-related failures during silicon bring-up and validation phases\nSkill Requirements\n5+ years of experience in SI/PI analysis for semiconductor packaging or high-speed PCB design\nStrong proficiency with industry-standard EM and circuit simulation tools:\nEM Solvers: Ansys HFSS, Ansys SIwave, Cadence Clarity 3D, Keysight ADS Momentum\nCircuit Simulation: Synopsys HSPICE, Cadence Spectre, Keysight ADS\nPDN Analysis: Ansys RedHawk, Cadence Voltus, Sigrity PowerDC/PowerSI\nDeep understanding of transmission line theory, Maxwell's equations, and S-parameter analysis\nExperience with high-speed interface protocols (PCIe, UCIe, HBM, DDR, Ethernet SerDes)\nProficiency in package stackup design, impedance control, and via transition optimization\nHands-on experience with measurement correlation (VNA, TDR/TDT, near-field scanning)\nProgramming/scripting skills (Python, MATLAB, Tcl) for automation and post-processing Preferred Qualifications\nExperience with 2.5D/3D advanced packaging technologies (CoWoS, EMIB, Foveros, hybrid bonding)\nFamiliarity with chiplet-based disaggregated architectures and die-to-die interconnect standards (UCIe, BoW)\nKnowledge of co-simulation methodologies (chip-package-board co-design)\nExperience with statistical analysis and Monte Carlo methods for manufacturing variation impact\nUnderstanding of thermal-aware electrical analysis (electro-thermal co-simulation)\nContributions to IEEE/DesignCon publications or industry standards committees (JEDEC, OIF, UCIe Consortium)\nExperience working with OSATs (ASE, Amkor, TSMC InFO/CoWoS) and substrate vendors\nOther Requirements\nTechnical Environment Domain EM Simulation Tools & Technologies Ansys HFSS, SIwave, Cadence Clarity 3D Solver, Keysight EMPro Circuit Simulation HSPICE, ADS, Spectre, SystemVue PDN Analysis Layout/Design Scripting Measurement Standards RedHawk-SC, Voltus, PowerSI, PowerDC Cadence APD/SiP, Synopsys IC Compiler, Mentor Xpedition Python, MATLAB, Tcl, Perl VNA (Keysight PNA-X), TDR (sampling scope), real-time oscilloscope PCIe 5.0/6.0, UCIe 1.1, HBM3/3E, DDR5, 112G/224G SerDes","description_format":"text","description_chars":3727,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Professional Services","Science & Engineering","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-28T08:26:33Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":2,"expected_fill_days":25,"reasons":["conf:2","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-31T05:58:55Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-8","json_url":"https://alion.io/job/hcltech-senior-technical-lead-post-silicon-validation-8.json","meta":{"generated_at":"2026-10-31T15:26:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24108,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-8"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-8"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-8"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-lead-post-silicon-validation-8\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-lead-post-silicon-validation-8"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3387611}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3387611},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}