{"id":2811986,"url":"https://alion.io/job/hcltech-senior-technical-lead-silicon-platform-validation-python-2","title":"Senior Technical Lead - Silicon Platform Validation, Python","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":158000,"max_usd":318000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1150},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Cadence Protium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Veloce","optional":false}],"status":"live","first_seen_at":"2026-10-18T09:46:44Z","employer_posted_date":"2026-10-18","last_verified_at":"2026-10-23T22:39:31Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Summary\nWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems - including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs - with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.\nKey Responsibilities\nPre-Silicon Validation\nDevelop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)\nCreate and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level\n\nVerify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior\nValidate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces\nPerform functional coverage analysis and drive coverage closure across IP blocks\nCollaborate with design and architecture teams on RTL debug, assertions, and specification reviews\nExecute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration\nPost-Silicon Validation\nBring up and validate SoC IPs on first silicon and platform boards\nDevelop and execute post-silicon test plans covering:Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions\nReset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection\n Ethernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping\n I/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing\n\nDebug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace tools\nPerform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams\nCharacterize IP performance under varying voltage, frequency, and temperature (VFT) conditions\nDevelop and maintain automated test frameworks for regression and production testing\nCollaborate with platform, firmware, BSP, and driver teams on system-level integration and debug\nGeneral\nAuthor and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases\nDevelop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis\nParticipate in silicon bring-up triage, failure analysis, and bug review meetings\nMentor junior engineers and drive process improvements in validation methodology\nInterface with IP vendors for third-party IP integration, compliance, and issue resolution\nSkill Requirements\nRequired Qualifications\nEducation: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\n Experience: 4-10+ years in SoC validation (pre-silicon and/or post-silicon)\nDeep understanding of SoC architecture and IP integration concepts\nOther Requirements\nnull","description_format":"text","description_chars":3316,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-18T09:46:44Z"}],"visa":[],"liveness":{"score":88,"band":"hot","label":"Hiring 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