{"id":3448426,"url":"https://alion.io/job/hcltech-senior-technical-lead-silicon-platform-validation-python-4","title":"Senior Technical Lead - Silicon Platform Validation, Python","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":2257},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AutoCAD","optional":false},{"name":"Cadence Allegro","optional":false},{"name":"HPC","optional":false},{"name":"Mentor Xpedition","optional":false}],"status":"live","first_seen_at":"2026-10-29T09:41:10Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-10-31T16:45:01Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Summary\nWe are seeking a highly motivated FCBGA Package Layout Engineer with expertise in advanced semiconductor package design and substrate layout development. The ideal candidate will be responsible for the complete package layout cycle, including bump map development, substrate routing, signal integrity considerations, manufacturability reviews, and collaboration with foundries, OSATs, substrate vendors, and cross-functional design teams. Key Responsibilities\nDevelop and maintain FCBGA package substrate layouts for high-performance computing, networking, AI, and ASIC products.\nCreate and optimize: o Die bump maps o Ball maps o Escape routing strategies o Power and ground distribution networks o RDL and substrate stack-ups\nPerform package floorplanning and routing using industry-standard EDA tools.\nWork closely with: o Silicon design teams o Signal Integrity (SI) engineers o Power Integrity (PI) engineers o PCB design teams o Assembly and manufacturing partners\nGenerate package documentation including: o Substrate drawings o Manufacturing deliverables Classification: Internal o Design rule specifications o Gerber/ODB++ outputs\nConduct layout reviews and design signoffs.\nDrive package optimization for: o Routability o Cost o Yield o Reliability o Electrical performance\nSupport package qualification activities and failure analysis investigations.\nInterface with OSATs and substrate suppliers to resolve design and manufacturing issues.\nEnsure compliance with package design rules and customer requirements. Required Qualifications\nBachelor's or Master's degree in: o Electronics Engineering o Electrical Engineering o Semiconductor Engineering o Related field\n5+ years of experience in semiconductor package design and layout.\nStrong understanding of: o Flip-Chip BGA (FCBGA) o Wirebond packages o High-density substrate technologies o Package assembly processes Classification: Internal\nExperience with: o Cadence Allegro Package Designer Plus (APD/APD+) o Cadence SiP Layout o Xpedition Package Designer (preferred) o AutoCAD (optional)\nKnowledge of: o Signal Integrity (SI) o Power Integrity (PI) o Thermal considerations o EM/IR analysis fundamentals\nFamiliarity with substrate technologies: o ABF substrates o Build-up layers o Coreless substrates o HDI structures Preferred Skills\nExperience with advanced packaging technologies: o 2.5D Interposer o CoWoS o EMIB o HBM integration o Chiplet-based architectures\nUnderstanding of: o DDR, PCIe, UCIe, Ethernet interfaces o High-speed SerDes routing o JEDEC packaging standards Classification: Internal\nAbility to develop package stack-ups and routing strategies for large body FCBGA packages (>50mm).\nExperience working directly with TSMC, Intel, Samsung, ASE, Amkor, SPIL, or other OSAT/substrate suppliers. Key Technical Skills\nBump map planning and optimization\nBall map design\nEscape routing\nPackage floorplanning\nSubstrate stack-up definition\nPower delivery network (PDN) design\nDesign rule checking (DRC)\nLVS verification\nSI/PI awareness\nManufacturing and assembly knowledge\nPackage reliability considerations Desired Soft Skills\nStrong analytical and problem-solving skills\nExcellent communication and presentation abilities\nAbility to lead package design reviews\nCross-functional collaboration skills\nCustomer-facing technical communication experience\nAbility to manage multiple projects simultaneously Nice-to-Have Experience\nAI accelerator packages\nHPC processors\nNetworking ASICs Classification: Internal\nData center products\nChiplet packaging architectures\nFCBGA packages with >5,000 signals and >10,000 substrate nets\nAdvanced packaging programs involving TSMC CoWoS, InFO, or Intel EMIB technologies\nKey Responsibilities\nDevelop and maintain FCBGA package substrate layouts for high-performance computing, networking, AI, and ASIC products.\nCreate and optimize: o Die bump maps o Ball maps o Escape routing strategies o Power and ground distribution networks o RDL and substrate stack-ups\nPerform package floorplanning and routing using industry-standard EDA tools.\nWork closely with: o Silicon design teams o Signal Integrity (SI) engineers o Power Integrity (PI) engineers o PCB design teams o Assembly and manufacturing partners\nGenerate package documentation including: o Substrate drawings o Manufacturing deliverables Classification: Internal o Design rule specifications o Gerber/ODB++ outputs\nConduct layout reviews and design signoffs.\nDrive package optimization for: o Routability o Cost o Yield o Reliability o Electrical performance\nSupport package qualification activities and failure analysis investigations.\nInterface with OSATs and substrate suppliers to resolve design and manufacturing issues.\nEnsure compliance with package design rules and customer requirements.\nSkill Requirements\nKey Technical Skills\nBump map planning and optimization\nBall map design\nEscape routing\nPackage floorplanning\nSubstrate stack-up definition\nPower delivery network (PDN) design\nDesign rule checking (DRC)\nLVS verification\nSI/PI awareness\nManufacturing and assembly knowledge\nPackage reliability considerations\nOther Requirements","description_format":"text","description_chars":5121,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Professional Services","Science & Engineering","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-29T09:41:10Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":1,"expected_fill_days":25,"reasons":["conf:2","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-31T05:58:55Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-senior-technical-lead-silicon-platform-validation-python-4","json_url":"https://alion.io/job/hcltech-senior-technical-lead-silicon-platform-validation-python-4.json","meta":{"generated_at":"2026-10-31T20:31:48Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":32301,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-senior-technical-lead-silicon-platform-validation-python-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-senior-technical-lead-silicon-platform-validation-python-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-senior-technical-lead-silicon-platform-validation-python-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-senior-technical-lead-silicon-platform-validation-python-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-senior-technical-lead-silicon-platform-validation-python-4"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3448426}},{"tool":"search_jobs","arguments":{"company":"hcltech.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3448426},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}