{"id":3150348,"url":"https://alion.io/job/hcltech-solution-director-2","title":"Solution Director","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":40000,"max_usd":76000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":82},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Ansys SIwave","optional":false},{"name":"Cadence Clarity 3D Solver","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"HPC","optional":false}],"status":"live","first_seen_at":"2026-10-23T11:53:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-24T17:33:32Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Summary\nJob Summary\nHCLTech is looking for an experienced SI/PI Packaging Design Architect with 15+ years of experience in signal integrity, power integrity and semiconductor package design. The ideal candidate will have strong expertise in high-speed interface design, package and substrate design, electromagnetic simulation, power delivery network optimization and advanced packaging technologies.\nThe candidate will work closely with silicon design, package design, PCB, system architecture and manufacturing teams to deliver high-performance semiconductor solutions that meet signal integrity, power integrity, thermal and reliability requirements.\nKey Responsibilities\nLead Signal Integrity (SI) and Power Integrity (PI) analysis for advanced semiconductor packages and high-speed interconnects.\nDrive package and substrate design optimization for high-performance computing, networking, AI/accelerator and SoC products.\nPerform pre-layout and post-layout SI/PI analysis, including crosstalk, insertion loss, return loss, impedance matching and power delivery network (PDN) analysis.\nLead package-level and package-to-board co-design activities, including bump maps, escape routing, substrate stack-up and interconnect optimization.\nPerform electromagnetic (EM) simulations and analyze high-speed interfaces such as PCIe, DDR, HBM, SerDes, Ethernet and other high-bandwidth interfaces.\nOptimize power distribution networks, decoupling capacitor placement, impedance profiles and simultaneous switching noise.\nCollaborate with package design, RTL/SoC, PCB, thermal, mechanical and manufacturing teams to resolve design challenges.\nDefine SI/PI design guidelines, simulation methodologies, sign-off criteria and design review processes.\nProvide technical leadership, mentor engineering teams and drive root-cause analysis for package- and system-level SI/PI issues.\nSupport design feasibility studies, technology evaluation, customer reviews and technical proposals.\nSkill Requirements\n15+ years of experience in semiconductor packaging, signal integrity, power integrity or package/board co-design.\nStrong knowledge of package substrate design, advanced packaging architectures and high-speed interconnect technologies.\nExpertise in SI/PI fundamentals, transmission lines, S-parameters, impedance control, crosstalk, reflections and PDN analysis.\nHands-on experience with 3D electromagnetic simulation, package extraction and SI/PI sign-off.\nExperience with advanced package technologies such as FC-BGA, 2.5D/3D IC, chiplets and HBM integration.\nKnowledge of high-speed protocols such as PCIe, DDR, HBM, SerDes and Ethernet.\nProficiency in relevant EDA tools such as Cadence Sigrity, Cadence Clarity 3D Solver, Ansys HFSS, Ansys SIwave or equivalent.\nUnderstanding of package stack-up, substrate materials, bump/ball assignments, parasitics, thermal constraints and manufacturing considerations.\nStrong problem-solving, technical communication and cross-functional collaboration skills.\nOther Requirements\nExperience leading SI/PI architecture, methodology development and technical sign-off for complex semiconductor packages.\nExposure to advanced packaging for AI, HPC, networking and high-bandwidth memory solutions.\nExperience working with global semiconductor customers and multidisciplinary engineering teams.","description_format":"text","description_chars":3324,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-23T11:53:27Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring 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