{"id":2521479,"url":"https://alion.io/job/hcltech-technical-architect-16","title":"Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":58000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-14T11:08:25Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-14T22:22:56Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Summary\nStandard Cell Characterization Architect/Manager to Lead a project and work on library characterization and model generation for advanced CMOS/FinFET technologies. The role involves generating high-quality Liberty (.lib) files, collaborating with design and layout teams, and supporting automation and validation of characterization flows.\nKey Responsibilities\nProvide technical leadership to a project and be responsible for overall delivery.\nPerform standard cell library characterization and generate:\nTiming, power, noise, and variation models\nAccurate Liberty (.lib) files\nDevelop understanding and support for:\nCircuit design and layout interactions\nView generation and automation flows\nExecute SPICE simulations and analyze characterization results\nGenerate extracted netlists from layout and perform characterization\nValidate libraries through QA checks and consistency verification\nWork with different collateral views:\nGDS, .lib, Verilog (.v), IBIS (.ibs), .db, etc.\nCollaborate with design, layout, and CAD teams for end-to-end delivery\nRequired Skills (Must-Have)\nShould be able to provide Technical Leadership for a project.\nShould be able to setup flow from scratch and mentor team members\nStrong understanding of CMOS and FinFET device characteristics\nStrong knowledge of digital circuit design (combinational & sequential)\nStrong understanding of SPICE simulation\nStrong knowledge of .lib generation and characterization flow\nStrong understanding of library characterization concepts, including:\nTiming, noise, power, and variation models\nSolid knowledge of:\nNLDM (Non-Linear Delay Model)\nCCS (Composite Current Source Model)\nLVF models\nStrong understanding of collateral views (GDS, .lib, Verilog, IBIS, .db)\nStrong understanding of:\nLibrary validation and quality checks (QA)\nStrong proficiency in scripting:\nLinux, Perl, Python, Tcl\nDesired Skills (Good-to-Have)\nMust be able to lead a project and team\nMust be able to setup flow from scratch\nStrong understanding of project and flow understanding\nKnowledge of deep submicron process challenges\nHands-on experience in advanced nodes (≤16nm, FinFET)\nGood communication and teamwork skills\nPositive learning attitude and adaptability\nEducation & Experience\nB.Tech / M.Tech in Electronics / VLSI / related field with 12-15 years of experience in Standard cell characterization / view generation\nKeywords\nStandard Cell Characterization, Liberty (.lib), SPICE Simulation, CMOS, FinFET, NLDM, CCS, LVF, Timing Models, Power Models, SiliconSmart, Liberate, View Generation, QA Validation\nKey Responsibilities\nStandard Cell Characterization Architect/Manager to Lead a project and work on library characterization and model generation for advanced CMOS/FinFET technologies. The role involves generating high-quality Liberty (.lib) files, collaborating with design and layout teams, and supporting automation and validation of characterization flows.\nKey Responsibilities\nProvide technical leadership to a project and be responsible for overall delivery.\nPerform standard cell library characterization and generate:\nTiming, power, noise, and variation models\nAccurate Liberty (.lib) files\nDevelop understanding and support for:\nCircuit design and layout interactions\nView generation and automation flows\nExecute SPICE simulations and analyze characterization results\nGenerate extracted netlists from layout and perform characterization\nValidate libraries through QA checks and consistency verification\nWork with different collateral views:\nGDS, .lib, Verilog (.v), IBIS (.ibs), .db, etc.\nCollaborate with design, layout, and CAD teams for end-to-end delivery\nRequired Skills (Must-Have)\nShould be able to provide Technical Leadership for a project.\nShould be able to setup flow from scratch and mentor team members\nStrong understanding of CMOS and FinFET device characteristics\nStrong knowledge of digital circuit design (combinational & sequential)\nStrong understanding of SPICE simulation\nStrong knowledge of .lib generation and characterization flow\nStrong understanding of library characterization concepts, including:\nTiming, noise, power, and variation models\nSolid knowledge of:\nNLDM (Non-Linear Delay Model)\nCCS (Composite Current Source Model)\nLVF models\nStrong understanding of collateral views (GDS, .lib, Verilog, IBIS, .db)\nStrong understanding of:\nLibrary validation and quality checks (QA)\nStrong proficiency in scripting:\nLinux, Perl, Python, Tcl\nDesired Skills (Good-to-Have)\nMust be able to lead a project and team\nMust be able to setup flow from scratch\nStrong understanding of project and flow understanding\nKnowledge of deep submicron process challenges\nHands-on experience in advanced nodes (≤16nm, FinFET)\nGood communication and teamwork skills\nPositive learning attitude and adaptability\nEducation & Experience\nB.Tech / M.Tech in Electronics / VLSI / related field with 12-15 years of experience in Standard cell characterization / view generation\nKeywords\nStandard Cell Characterization, Liberty (.lib), SPICE Simulation, CMOS, FinFET, NLDM, CCS, LVF, Timing Models, Power Models, SiliconSmart, Liberate, View Generation, QA Validation\nSkill Requirements\nnull\nOther Requirements\nnull","description_format":"text","description_chars":5180,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems 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