{"id":3150324,"url":"https://alion.io/job/hcltech-technical-architect-73","title":"Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-10-23T11:53:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-24T13:04:26Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Summary\nA GPIO (General-Purpose Input/Output) Circuit Design Engineer is responsible for designing, optimizing, and verifying the custom mixed-signal and digital I/O structures that bridge an integrated circuit (IC) or System-on-Chip (SoC) core logic with the outside world. This role involves transistor-level design, electrostatic discharge (ESD) protection integration, and power-performance-area (PPA) optimization on advanced process nodes.\nJob Summary\nDepartment: Technology Foundation / IO team\n Experience Level: Mid to Senior Level (typically 7+ years in semiconductor IP design)\nCore Focus: Transistor-level design of I/O buffers, level shifters, receivers, and reliability circuits. \nKey Responsibilities\nKey Responsibilities\n1. Circuit Design & Optimization\nDesign and optimize standard and specialized GPIO circuits (including push-pull/open-drain output buffers, Schmitt triggers, level shifters, and programmable pull-up/pull-down resistors). \nEnsure proper voltage domain transitions using level-up and level-down shifters between low-voltage core logic (e.g., 0.8V) and higher-voltage I/O rings (e.g., 1.8V or 3.3V). \nManage multi-voltage signaling architectures and high-impedance (Hi-Z) tri-state buffer controls. \n2. Simulation & Verification\nPerform transistor-level circuit simulations (HSPICE/Spectre) to analyze performance, leakage, and robustness across process, voltage, and temperature (PVT) corners.\nRun static and dynamic reliability checks, including electromigration (EM), IR drop, and electrical overstress (EOS). \n3. Layout, ESD & Reliability Integration\nCollaborate closely with layout engineers to ensure matching, parasitic minimization, and strict Design Rule Checking (DRC) / Layout Versus Schematic (LVS) compliance.\nCo-design and verify Electrostatic Discharge (ESD) and latch-up protection structures to guarantee foundry reliability standards. \n4. Cross-Functional Collaboration\nInterface with SoC integration, RTL design, and digital verification teams to support pad ring assembly and core-to-I/O boundary timing closure.\nParticipate in silicon bring-up, lab debugging, and model-to-silicon validation correlation. \nSkill Requirements\nTechnical Domain: Strong fundamentals in CMOS mixed-signal circuit design and deep sub-micron device physics.\n EDA Tools: Proficiency with industry-standard IC design tools such as Cadence Virtuoso, Synopsys HSPICE, or Siemens EDA (Mentor Graphics) platforms.\n Languages & Scripting: Familiarity with hardware description languages (Verilog/VHDL) and scripting languages (Python, Tcl, Perl) to automate design flows.\n Standards & Protocols: Knowledge of JEDEC standards, GPIO control registers, and bus interfaces (like AMBA APB) is highly preferred\nOther Requirements\n Education: Bachelor’s or Master’s degree in Electronics/Electrical Engineering or a related technical discipline.","description_format":"text","description_chars":2867,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-10-23T11:53:27Z"}],"visa":[],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":0,"expected_fill_days":31,"reasons":["conf:2","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-technical-architect-73","json_url":"https://alion.io/job/hcltech-technical-architect-73.json","meta":{"generated_at":"2026-10-24T15:42:40Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22608,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":225},"rest":"https://alion.io/mcp/rest/get_company?id=225"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhcltech-technical-architect-73"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhcltech-technical-architect-73"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhcltech-technical-architect-73"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hcltech-technical-architect-73\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhcltech-technical-architect-73"}]}