{"id":1223240,"url":"https://alion.io/job/hcltech-technical-architect","title":"Technical Architect","company":{"id":225,"name":"HCLTech","domain":"hcltech.com","url":"https://alion.io/company/hcltech","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Python","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-09-25T13:02:39Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-27T02:34:24Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Summary\nCandidates with 8 to 14 years' experience is mandatory\nBachelor's or Master's degree in Electronics & Communication Engineering (ECE),\nElectrical Engineering (EE), VLSI Design, or a closely related field\"\nDefine ASIC/SoC verification strategy:\nGood understanding of ASIC/SoC life cycle\nFull chip testplan development:\nHas participated in multiple ASIC/SoC verification till tapeout stage\nFull chip TB Architecture definition\nExperience writing ASIC/SoC testplans\nUVM based testbench development\n1.Experience in ASIC/SoC Testbench definition\n2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).\"\nSV functional coverage, Assertions coding\n1.Expertise & hands-on experience in OVM/UVM methodologies using SV\n2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.\nKey Responsibilities\nC based TB development\n1. Experience in developing TB components for SOC with C, SV\nTest case development, coding, execution, bug analysis\n1. Experience in developing TB components, including functional coverage implementation and assertion coding\n2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.\n3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.\n4. Experience in SOC C based tests coding & debugging\nGate Level Simulation\nExperience in Gate level simulation & netlist debugging\nRegressions, coverage analysis\nExperience in regression failure analysis, Functional and Code Coverage closure\nOwn and execute verification closure\nExperience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.\nExperience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.\nExperience in Document test plans, micro-architecture specifications, and verification results for team reviews\nSkill Requirements\nCore Technical Skills\nProven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.\nExpert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).\nDigital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.\nProcessor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.\"\nTools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.\nProtocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).\"\nScripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.\nOther Requirements\nSoft Skills\nStrategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.\nInfluence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.","description_format":"text","description_chars":3409,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","IT Outsourcing & Dedicated Teams","Systems Integrators"],"lifecycle":[{"event":"open","at":"2026-09-25T13:02:39Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":27,"reasons":["conf:27","velocity","win:early","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/hcltech-technical-architect","json_url":"https://alion.io/job/hcltech-technical-architect.json","meta":{"generated_at":"2026-09-29T01:52:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1559,"day_limit":5000,"remaining_today":3441,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}