{"id":1164357,"url":"https://alion.io/job/hewlett-packard-enterprise-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":5292,"name":"Hewlett Packard Enterprise","domain":"hpe.com","url":"https://alion.io/company/hewlett-packard-enterprise","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":114,"ghost_share":0,"stale_share":0.956,"repost_share":0,"time_to_fill_p50_days":35,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":153500,"max":310500,"currency":"USD","period":"year","gross":null,"usd_annual":310500},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"AI Agents","optional":true},{"name":"Cadence JasperGold","optional":true},{"name":"CI/CD","optional":true},{"name":"Formal Verification","optional":true},{"name":"Synopsys VC Formal","optional":true},{"name":"TCP/IP","optional":true}],"status":"live","first_seen_at":"2026-09-16T00:00:00Z","employer_posted_date":"2026-09-16","last_verified_at":"2026-10-20T15:28:00Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Senior Design Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.Who We Are:\nHewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.\nJob Description:\nWe are seeking a talented and drivenSeniorDesign Verification Engineer with specialized knowledgeand experienceinemulation-based verification to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.\nResponsibilities\nDevelop and execute verification plans for IP-level and system-level designs.\n\nBuild, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.\n\nDevelop and run directed and constrained-random test cases to achieve functional and code coverage goals.\n\nSet up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, SynopsysZeBu, Mentor Veloce) for system-level verification and performance validation.\n\nCollaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.\n\nDebug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.\n\nDevelop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.\n\nDrive coverage closure and generate verification sign-off reports.\n\nSupport software and firmware teams with early bring-up activities on emulation platforms.\n\nContinuously improve verification processes, flows, and infrastructure.\n\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.\n\n5 - 8 years of professional experience in design verification of digital/mixed-signal designs.\n\nStrong proficiency inSystemVerilog andUVM methodology.\n\nHands-on experience with emulation-based verification platforms (e.g., Cadence Palladium, SynopsysZeBu, or Mentor Veloce).\n\nSolid understanding of digital design concepts including RTL design, synthesis constraints, and timing.\n\nExperience with constrained-random verification, functional coverage, and code coverage-driven methodologies.\n\nProficiency in debugging complex hardware designs using simulation and emulation tools.\n\nFamiliarity with scripting languages such asPython,Perl, orTCL for automation and flow development.\n\nStrong analytical and problem-solving skills with excellent attention to detail.\n\nPreferred Qualifications\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field.\n\nExperience with networking protocols such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.\n\nKnowledge ofcommunication and interface protocols including AXI, AHB, APB, AMBA, I2C, SPI, or UART.\n\nExperience with formal verification tools and techniques (e.g.,JasperGold, VC Formal).\n\nFamiliarity withFPGA prototyping platforms and flows.\n\nExperience with power-aware verification (UPF/CPF).\n\nPrior exposure toSoC-level verification or full-chip integration verification.\n\nKnowledge of processor architectures (ARM, RISC-V, x86) and software-driven verification techniques.\n\nExperience with continuous integration (CI) and regression management frameworks.\n\nFamiliarity withAI/ML application and architectures and experience, such as, creating Gen AI skills, marketplace, agentic applications, etc.\n\nPublished work or patentsin the area ofdesign verification is a plus.\n\nAccessibility\nHPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.\nNote: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.\nWhat We Can Offer You:\nHealth & Wellbeing\nWe strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.\nPersonal & Professional Development\nWe also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.\nUnconditional Inclusion\nWe are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.\nLet's Stay Connected:\nFollow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.\n#unitedstatesJob:\nEngineeringJob Level:\nTCP_04\"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.- United States of America: Annual Salary USD 153,500 - 310,500 in California\nThe listed salary range reflects base salary. Variable incentives may also be offered.\"\nInformation about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html\nHPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBTemployer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.\nHewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.\nHPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.\nRecruitment Fraud Alert\nWe have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.\nAll legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. 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