{"id":163073,"url":"https://alion.io/job/hp-inc-senior-asic-design-engineer","title":"Senior ASIC Design Engineer","company":{"id":72,"name":"HP Inc.","domain":"hp.com","url":"https://alion.io/company/hewlett-packard","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":203,"ghost_share":0,"stale_share":0.695,"repost_share":0.005,"time_to_fill_p50_days":22,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Vancouver, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":116150,"max":182400,"currency":"USD","period":"year","gross":null,"usd_annual":182400},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"GitHub","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false},{"name":"Copilot","optional":true},{"name":"LLM","optional":true}],"status":"live","first_seen_at":"2026-07-29T00:00:00Z","employer_posted_date":"2026-07-29","last_verified_at":"2026-10-28T13:18:03Z","board_verified":true,"closed_at":null,"days_open":91,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":91},"description":"Senior ASIC Design EngineerDescription -\nHP is the world’s leading printing company. We are looking for innovators who are ready to make a purposeful impact. You will be a member of the R&D digital Application-Specific Integrated Circuit (ASIC) design team that develops the main controller with critical HP proprietary intellectual property that separates HP printers from the rest of the competitions. You will work with internal and external partners to deliver industry-leading embedded solutions for future HP printers.\nOur new Vancouver, Washington site expands HP's presence in the Pacific Northwest and serves as a hub for engineering innovation and product development. This location brings together talented engineers working on next-generation technologies that power HP's industry-leading print and imaging solutions. As part of our Imaging & Print organization, you'll help develop advanced imaging capabilities that enhance performance, quality, and customer experiences across HP's enterprise product portfolio.\nResponsibilities:\nLead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification.\n\nProactively work with other team members and partners to align on specifications, drive reviews, and complete documentation.\n\nManage and expand relationships with internal and external development partners.\n\nBe a key contributor to ASIC roadmaps and future innovation.\n\nLead cross-discipline task force to triage product HW & FW integration issues to deliver robust solutions.\n\nContribute to key areas of Inkjet and Laserjet print architecture and data path requirements.\n\nBe a key contributor to co-development activities to help prototype ASIC designs in FPGA or other software models to support pre-silicon firmware development and verification.\n\nDrive design methodology and tool automation work as needed.\n\nEducation and Experience Required:\nBS or MS degree in electrical engineering or equivalent with focus on VLSI design experience\n\n8 -10 years of ASIC or SOC design and development experience\n\nKnowledge and Skills:\nDeep knowledge of submicron semiconductor technology.\n\nDeep knowledge of embedded system design, verification, and product development lifecycle.\n\nVery familiar with digital ASIC/SOC design flow from RTL to silicon characterization\n\nVery familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.\n\nVery familiar with design and programming languages: Verilog, SV, Python, Perl, C, C++, etc.\n\nVery familiar with code base management method including subversion, git, GitHub, etc.\n\nExcellent analytical and problem-solving skills.\n\nExcellent written and verbal communication skills, ability to negotiate design features and options\n\nWorking knowledge of electronic components, PCA designs and use of test equipment\n\nDeep knowledge and domain know-hows in one or more areas below is a big plus.\nLaserjet printing technology\n\nARM microprocessor subsystem\n\nMemory and storage subsystem (DDR, Flash, eMMC, etc.)\n\nDesign database management, scripting and other design flow automation\n\nProficiency in applying AI Copilot (LLM-based tools) to accelerate ASIC design, verification, and engineering productivity.\n\nThe pay range for this role is$116,150 to $182,400 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.\nBenefits:\nHP offers a comprehensive benefits package for this position, including:\nHealth insurance\n\nDental insurance\n\nVision insurance\n\nLong term/short term disability insurance\n\nEmployee assistance program\n\nFlexible spending account\n\nLife insurance\n\nGenerous time off policies, including;\n\n4-12 weeks fully paid parental leave based on tenure\n\n11 paid holidays\n\nAdditional flexible paid vacation and sick leave (US benefits overview)\n\nThe compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.\nJob -\nEngineeringSchedule -\nFull timeShift -\nNo shift premium (United States of America)Travel -\nNoRelocation -\nYesEqual Opportunity Employer (EEO)-\nHP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).\nPlease be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.\nFor more information, review HP’sEEO Policy or read about your rights as an applicant under the law here: “ Know Your Rights: Workplace Discrimination is Illegal \"","description_format":"text","description_chars":5302,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Dental insurance","Equity","Health insurance","Life insurance","Parental leave","Vision insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Laptops","Computer Peripherals","3D Printers & Additive Manufacturing","Printers & Scanners"],"lifecycle":[{"event":"open","at":"2026-07-29T00:00:00Z"}],"visa":[],"liveness":{"score":9,"band":"cold","label":"Long shot","p_open":1,"p_active":0.314,"p_room":0.28,"age_days":91,"expected_fill_days":22,"reasons":["conf:3","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-28T05:59:10Z"},"pay":{"stated_usd_annual":182400,"is_top_pay":false},"html_url":"https://alion.io/job/hp-inc-senior-asic-design-engineer","json_url":"https://alion.io/job/hp-inc-senior-asic-design-engineer.json","meta":{"generated_at":"2026-10-28T13:19:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17923,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":72},"rest":"https://alion.io/mcp/rest/get_company?id=72"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fhp-inc-senior-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fhp-inc-senior-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fhp-inc-senior-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/hp-inc-senior-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fhp-inc-senior-asic-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":163073}},{"tool":"search_jobs","arguments":{"company":"hp.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":163073},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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