{"id":2532190,"url":"https://alion.io/job/ics-senior-robotics-middleware-engineer","title":"Senior Robotics Middleware Engineer","company":{"id":1816005,"name":"ICS","domain":"ics.com","url":"https://alion.io/company/ics-com","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"CATS","truth_index":null},"role":"Robotics","role_family":"Robotics","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Wilmington, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":123000,"max_usd":247000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":201},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cyclone DDS","optional":false},{"name":"Fast DDS","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"PyTorch","optional":false},{"name":"PyTorch C++","optional":false},{"name":"ROS","optional":false},{"name":"TensorRT","optional":false},{"name":"Zenoh","optional":false},{"name":"CUDA","optional":true},{"name":"CUDA Toolkit","optional":true},{"name":"Nav2","optional":true},{"name":"ROS2","optional":true}],"status":"live","first_seen_at":"2026-10-14T13:06:12Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T19:23:49Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Location/Eligibility: This is a contract position based in Massachusetts. You must be able to commute to the Wilmington area onsite at least 3 days a week. For this contract, there is no visa sponsorship available.We are seeking a high-caliber Robotics Middleware Engineer to evaluate, prototype, and build our next-generation communication infrastructure. In this role, you will move beneath the standard application layer to optimize high-throughput, shared-memory messaging on NVIDIA Jetson-class hardware. You will be the architect responsible for eliminating communication bottlenecks, ensuring that heavy ML inference and sensor streams flow through the robot's \"nervous system\" with zero latency.\nCore Responsibilities\nNext-Gen Middleware Evaluation: Lead a comprehensive build-vs-adopt evaluation of Zenoh as a robotics transport layer, analyzing its performance both standalone and as an RMW layer under ROS 2. Deliver architectural recommendations backed by rigorous benchmarks.\n\nData Path Optimization: Optimize zero-copy and shared-memory messaging paths on ARM/Jetson architectures, focusing heavily on memory layout optimization, serialization efficiency, and transport tuning.\n\nPerformance Benchmarking: Design and execute benchmarking suites to measure latency, throughput, and CPU/GPU overhead, systematically comparing new architectures against our current data path.\n\nML & Sensor Integration: Support the full-stack team by ensuring low-latency integration for heavy workloads, including vision sensors (Stereo/RGBD), IMUs, and ML model inference pipelines (PyTorch, TensorRT, JIT).\n\nTechnical Requirements (Must-Have)\nROS 2 & DDS Internals: Deep, hands-on experience with ROS 2 middleware (RMW) layers and the inner workings of DDS implementations (e.g., Cyclone DDS, Fast DDS).\n\nAdvanced Transports: Proven experience with Zenoh or comparable modern pub/sub architectures designed for high-performance edge computing (e.g., eCAL, iceoryx).\n\nSystems Programming: Exceptional proficiency in Modern C++ and deep familiarity with shared-memory Inter-Process Communication (IPC).\n\nEmbedded Profiling: Hands-on experience with performance profiling and bottleneck identification on embedded Linux and ARM architectures.\n\nCore Languages: Strong proficiency in Python is required alongside your primary C++ systems skill set.\n\nPreferred Qualifications (Nice-to-Have)\nNVIDIA Jetson Ecosystem: Direct experience optimizing software for Jetson-class hardware.\n\nHardware-Aware Memory: Understanding of GPU/CUDA memory awareness, unified memory architectures, and avoiding host-to-device copy overhead.\n\nReal-Time Systems: Practical knowledge of real-time Linux patches (PREEMPT_RT) and deterministic software design.\n\nExperiencing tuning or customizing the ROS 2 Nav2 stack or working with vSLAM algorithms.\n\nAre you the right fit?\nYou thrive in high-velocity environments where engineering decisions directly impact hardware performance. You enjoy digging into network packets, memory dumps, and kernel-level timing to squeeze microsecond efficiencies out of resource-constrained systems. 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