ASIC Design Engineer – Memory Controller
Confirmed on the employer's own hiring board on Oct 28, 2026. First seen by Alion on Jun 29, 2026. Iluvatar CoreX scores C on the Alion truth index.
Responsibilities
1. Develop micro-architecture, write micro-architecture spec and other documents.
2. Write RTL code, meet the function target and have good performance/power/area efficiency.
3. Apply low power, DFT, DFD and other digital design techniques.
4. Work with DV team to improve test plan and debug failed tests.
5. Clean Lint, timing and other issues.
6. Participate in silicon debugging.
Qualifications
1. Master in electrics or computer engineering.
2. At least 5 years working experience in ASIC logic design.
3. Familiar with DRAM structure and standards (DDR/LPDDR/GDDR/HBM), DFI interface protocol.
4. Experience with memory controller/ DRAM controller design.
5. Experience with memory controller performance debug and post silicon memory controller bring up.
6. Familiar with front-end EDA tools and flows.