{"id":1658177,"url":"https://alion.io/job/infineon-technologies-principal-engineer-design-3","title":"Principal Engineer Design","company":{"id":51757,"name":"Infineon Technologies","domain":"infineon.com","url":"https://alion.io/company/infineon-technologies","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Eightfold","truth_index":{"grade":"B","score":81,"open_postings":203,"ghost_share":0,"stale_share":0.759,"repost_share":0,"time_to_fill_p50_days":53,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":13,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Formality","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false}],"status":"live","first_seen_at":"2026-07-17T10:21:37Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-23T22:15:12Z","board_verified":true,"closed_at":null,"days_open":98,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":98},"description":"#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?\nYour role\nKey responsibilities in your new role\nAs\nan engineer, Timing Closure, and Constraints Coding/Validation Engineer, you\nwill own the architectural timing intent, constraint hygiene, and complete\ntiming sign-off for complex, multi-million gate SoCs. You will drive multi-mode\nmulti-corner (MMMC) timing closure from block-level implementation up to\nfull-chip integration. A core focus of this role is using advanced optimization\ntools to fix critical setup, hold, transition and crosstalk violations across\nboth functional and complex DFT modes (Scan, At-Speed, MBIST etc).\n Timing Closure & ECO Sign-off: Lead and execute block-level and full-chip flat/hierarchical timing closure across advanced process nodes. Generate engineering change orders (ECOs) to fix setup, hold, max transition, and signal integrity violations\n Tool-Driven Optimization: Demonstrate expert mastery over automated ECO fixing tools (Tweaker, PT DMSA/Primeclosure, Cadence Tempus) drive rapid convergence of complex bottleneck violation\nMulti-Signoff STA Infrastructure: Architect, set up, and execute robust MMMC sign-off environments using Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus. Ensure complete correlation across different timing engines\nHierarchical Constraint Management: Architect, generate, and maintain clean SDC files at both the Block/IP level and the Full-Chip Top level. Manage constraint promotion, demotion, and validation\n Signal Integrity & Noise Analysis: Strong understanding of crosstalk-induced noise, glitch propagation, signal electromigration (Signal EM), and managing reconvergent timing paths affected by crosstalk delay\n DFT Mode Timing Validation: Define, audit, and validate constraints across multiple operational modes, specifically targeting Scan Shift & Capture, At-Speed Testing, Memory BIST (MBIST), and Logic BIST (LBIST) concurrent execution modes\n Cross-Functional Leadership: Collaborate with DFT Engineers to resolve test mode constraints, RTL Designers to fix structural CDC/RDC violations, and P&R Teams to guide placement, clock-tree synthesis (CTS), and routing optimization\nAutomation & Flow Development: Write advanced, production-grade Tcl scripts for PrimeTime/Tempus environments\nUtilize Python or Perl to build regression suites, analyze timing violations, and compare SDC variations \nYour profile\nQualifications and skills to help you succeed \nBachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.\nMinimum 13+ years of relavent experience in STA full chip \n Core Tool Expertise (Mandatory):Sign-off STA: Synopsys PrimeTime (PT/PT-PX) and Cadence Tempus.\n Timing Closure / ECO:Cadence Tempus, Synopsys PrimeTime/PrimeClosure & Tweaker\n Constraints Validation:Synopsys TCM/GCA, Ausdia TimeVision, SpyGlass Constraints, or Cadence CCD\n\nRun strict constraints verification using industry-standard tools (Synopsys TCM, SpyGlass Constraints, or Cadence CCD) to eliminate unconstrained paths, incorrect clock-gating checks, and conflicting case analysis settings between functional and DFT model\nHands-on experience reading, writing, and parsing Unified Power Format (UPF) constraints to validate low-power design architectures (e.g., power-gating, isolation cells, retention registers, and level-shifter placement\nFamiliarity with Logic Equivalency Checking using industry tools like Cadence Conformal LEC or Synopsys Formality to verify that optimization/ECO steps maintain functional equivalence \nDeep understanding of advanced node variation models (POCV/LVF), temperature inversion, crosstalk/noise analysis, and hierarchical top-level clock distribution networks\nSolid comprehension of DFT architecture, test clock structures, multiplexer-heavy clock networks, and asynchronously driven test logic\nExpert proficiency in Tcl (highly critical for runtime timing script customization) and Python/Perl for automated data mining and constraint auditing\n#WeAreIn for driving decarbonization and digitalization.\nAs a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.\nAre you in?\nWe are on a journey to create the best Infineon for everyone.\nWe strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.\nOur hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.\nPlease let your recruiter know if you need any accommodations during the interview process.\nLearn more about our various contact channels and about Diversity & Inclusion at Infineon.\nGowri Shenoy\nhttps://www.linkedin.com/in/gowri-shenoy-33894217/","description_format":"text","description_chars":5124,"description_truncated":false,"requirements":{"experience_years_min":13,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-10-02T02:31:58Z"}],"visa":[],"liveness":{"score":16,"band":"cold","label":"Long shot","p_open":1,"p_active":0.456,"p_room":0.36,"age_days":97,"expected_fill_days":53,"reasons":["conf:2","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/infineon-technologies-principal-engineer-design-3","json_url":"https://alion.io/job/infineon-technologies-principal-engineer-design-3.json","meta":{"generated_at":"2026-10-24T02:08:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3475,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":51757},"rest":"https://alion.io/mcp/rest/get_company?id=51757"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Finfineon-technologies-principal-engineer-design-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Finfineon-technologies-principal-engineer-design-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Finfineon-technologies-principal-engineer-design-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/infineon-technologies-principal-engineer-design-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Finfineon-technologies-principal-engineer-design-3"}]}