Staff Engineer Digital Verification

Your Role

Key responsibilities in your new role

• Create and define verification plans
• Develop verification environments for our ICs using Universal Verification Methodology (UVM)
• Draw on test scenarios using SystemVerilog
• Verify functionality using the Constrained Random approach
• Develop assertions in SystemVerilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies
• Provide proactive support to users of our verification flow environment
• Be responsible for our verification methods

Your Profile

Qualifications and skills to help you succeed

• Bachelor's Degree or above in Electrical Engineering, Computer Science or a similar academic discipline
• At least 3 years of experience in Metric Driven Verification (digital and/or mixed-signal)
• Capabilities and hands-on experience in working with microcontroller-based ICs, as well as security and safety requirements
• Excellent know-how with UVM especially using SystemVerilog
• Knowledge of firmware and RTL design (VHDL)
• (Preferred) Knowledge of Cadence verification software

Contact:

[email protected]

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