{"id":4081344,"url":"https://alion.io/job/intel-3dic-device-development-engineer","title":"3DIC Device Development Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":104,"ghost_share":0.029,"stale_share":0.538,"repost_share":0.038,"time_to_fill_p50_days":30,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States","Santa Clara, United States","Phoenix, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Design of Experiments","optional":true},{"name":"TCAD","optional":true}],"status":"live","first_seen_at":"2026-11-10T00:00:00Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-11T17:24:48Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Details:\nJob Description:\nAbout the Team\nManufacturing Development and Customer Engineering (MDCE) serves as the critical bridge between Technology Development (TD) and High Volume Manufacturing (HVM) within Intel Foundry. The organization is responsible for transitioning leading-edge technologies from development and qualification into high-yield production while enabling successful deployment for foundry customers.\nThe MDCE Device Team is expanding its 3DIC device engineering capabilities and is seeking an experienced engineer to drive device understanding and optimization for advanced 3D integration technologies.\nPosition Overview\nAs a 3DIC Device Development Engineer, you will be responsible for understanding, characterizing, and modeling the impact of advanced 3D integration technologies on transistor and passive device performance. Technologies such as through-silicon vias (TSVs), hybrid bonding, active base die architectures, wafer thinning, and backside power delivery introduce new mechanical, thermal, and electrical interactions that influence device behavior, variability, and reliability.\nIn this role, you will transform complex silicon data into actionable insights, design rules, device collateral, and customer-ready guidance that support next-generation products including AI accelerators, high-performance computing solutions, and high-bandwidth memory (HBM) platforms.\nKey Responsibilities\nResponsibilities include, but are not limited to:\nCharacterize and model the impact of advanced 3D integration technologies, including TSVs, hybrid bonding, wafer thinning, and backside processing, on device performance metrics such as mobility, threshold voltage (Vt), leakage, matching, and variability.\nEvaluate stress, thermal, and electrical coupling effects, including keep-out zone (KOZ) behavior and device interactions within complex 3D stacks.\nDefine and develop device and passive test structures to study 3DIC effects, including TSV proximity, KOZ, guard ring, resistor, and capacitor structures.\nDrive electrical test (e-test) strategy, data collection, and silicon analysis to accelerate technology learning and optimization.\nProvide device characterization inputs that enable design rule development, compact models, PDKs, and 3D design kit releases in collaboration with Design Enablement teams.\nPartner closely with Process Integration, Packaging, Assembly, Reliability, Yield, and Program Management organizations to identify, troubleshoot, and resolve device-related issues.\nEvaluate customer requirements for analog, mixed-signal, RF, and high-speed I/O devices within 3D architectures, assessing technical feasibility, risk, and implementation timelines.\nSupport technology qualification and manufacturing readiness activities, including device targeting, monitoring strategies, yield improvement efforts, and excursion management.\nCommunicate complex technical findings and recommendations to engineering, business, and customer stakeholders.\nWhat We Are Looking For\nThe successful candidate will demonstrate:\nDeep understanding of CMOS device physics and the impact of process, stress, and thermal effects on device performance.\nStrong analytical and problem-solving skills, including data science, statistical analysis, and scripting capabilities.\nExcellent written and verbal communication skills with the ability to explain complex technical concepts to diverse audiences.\nProven ability to influence and collaborate across device, process, packaging, manufacturing, and design organizations.\nStrong ownership mindset, technical curiosity, and a passion for developing innovative solutions in advanced semiconductor technologies.\nQualifications:\nThe Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications\nMaster's degree in Electrical Engineering, Physics, Materials Science, or a related field with 4+ years of industry experience, in semiconductor device engineering, process integration, advanced packaging, or related technology development.\n3+ years of experience in advanced CMOS device characterization and electrical parametric (e-test) data analysis.\nHands-on experience with one or more advanced packaging and 3D integration technologies, including:Through-silicon vias (TSVs)\nHybrid bonding\n\nWafer-to-wafer or die-to-wafer bonding\n\nMicro-bump technologies\n\nWafer thinning\n\nBackside power delivery\n\nPreferred Qualifications\nPhD in Electrical Engineering, Physics, Materials Science, or a related field.\nExperience analyzing stress and thermal interactions affecting device behavior, including TSV keep-out zones and chip-package interaction effects.\nExpertise in test structure development, design of experiments (DOE), and e-test program implementation.\nKnowledge of device modeling, design rule development, PDK generation, or design technology co-optimization (DTCO).\nExperience using TCAD and/or finite element analysis tools for stress, thermal, or device simulations.\nUnderstanding of semiconductor reliability mechanisms, including electromigration (EM), time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), and bonding interface reliability.\nExperience with advanced node technologies, including FinFET and Gate-All-Around (GAA) devices.\nSemiconductor foundry experience with direct customer engagement and technical support.\nExperience supporting technology transfer and production ramp in high-volume manufacturing environments.\nJoin us in shaping the future of semiconductor innovation through advanced 3D integration technologies that enable the next generation of AI, HPC, and memory solutions.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nUS, Arizona, Phoenix, US, California, Santa ClaraPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $136,900.00-269,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":8081,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-11T17:24:48Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 2,029 · green card filings: 490","filings_12m":2029,"filings_prev_12m":3014,"green_card_filings_12m":490,"median_offered_wage_usd":134832,"route":null,"cap_exempt":false,"checked_at":"2026-11-11T07:38:50+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":1,"expected_fill_days":30,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-11-11T18:29:13Z"},"pay":null,"html_url":"https://alion.io/job/intel-3dic-device-development-engineer","json_url":"https://alion.io/job/intel-3dic-device-development-engineer.json","meta":{"generated_at":"2026-11-11T18:29:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":35550,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-3dic-device-development-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-3dic-device-development-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-3dic-device-development-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-3dic-device-development-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-3dic-device-development-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4081344}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4081344},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}