{"id":3593962,"url":"https://alion.io/job/intel-ai-silicon-performance-modeling-and-analysis-engineer","title":"AI Silicon Performance Modeling and Analysis Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":94,"ghost_share":0.032,"stale_share":0.564,"repost_share":0.043,"time_to_fill_p50_days":30,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":164000,"max_usd":303000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":6,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"Grafana","optional":true},{"name":"Plotly","optional":true},{"name":"Power BI","optional":true},{"name":"Tableau","optional":true}],"status":"live","first_seen_at":"2026-10-31T00:00:00Z","employer_posted_date":"2026-10-31","last_verified_at":"2026-11-03T12:22:44Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nAbout the Role and Team\nThe AI Silicon Architecture and Performance Engineering team is responsible for developing and maintaining performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These models are a critical component of the product development process, providing early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities long before silicon availability.\nWe are seeking a highly experienced and motivated engineer to drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement activities. The candidate will work closely with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize key AI silicon subsystems that determine overall platform scalability and performance.\nThe role focuses on performance modeling and analysis of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The successful candidate will leverage SystemC/TLM-based modeling methodologies to generate actionable insights that directly influence architecture and product decisions.\nThis position requires a unique combination of software development expertise, architecture understanding, analytical problem solving, and cross-functional technical leadership. The engineer will be expected to independently drive complex technical initiatives while serving as a trusted performance expert across multiple organizations.\nKey Responsibilities:\nAI Silicon Performance Model Development\nImplement new architectural features and capabilities based on evolving product requirements.\nImprove model fidelity, scalability, maintainability, and simulation performance.\nPerform detailed debugging and root-cause analysis of model issues and performance anomalies.\nContribute to the evolution of modeling infrastructure, methodologies, and best practices.\nDevelop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems.\nDrive modeling of key architectural components including:\nSoC fabrics and on-chip communication networks\nMemory controllers and memory subsystem behavior\nScale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray, or pod\nScale-out controllers and fabrics enabling communication across nodes, racks, and larger AI clusters\nHost CPU to accelerator memory paths\nLocal, host, and remote memory access paths\nEnd-to-end data movement architectures\n\nFunctional Validation and Model Correlation:\nDefine and execute comprehensive validation strategies to ensure correctness and architectural accuracy of performance models.\nDevelop validation plans, regression suites, coverage methodologies, and quality metrics.\nCorrelate modeled behavior against architectural expectations, reference simulations, performance projections, and available hardware measurements.\nInvestigate and resolve discrepancies between expected and observed behavior.\nEstablish robust validation frameworks that improve stakeholder confidence in model-generated performance projections.\nContinuously improve validation methodologies and model quality.\nAI Silicon Performance Characterization and Architectural Analysis:\nDesign and execute performance studies covering a wide range of workloads, traffic patterns, and system configurations.\nAnalyze performance of communication fabrics, memory systems, and data movement paths under representative AI workloads.\nEvaluate bandwidth utilization, latency characteristics, congestion behavior, traffic distribution, buffering efficiency, and resource utilization.\nCharacterize interactions across local memory, host memory, and remote memory domains.\nAssess scalability of scale-up and scale-out architectures across increasingly larger deployment footprints.\nIdentify performance bottlenecks and quantify their impact on overall system throughput and efficiency.\nConduct architectural tradeoff studies to evaluate alternative design approaches.\nProvide performance-driven recommendations that influence architecture and product decisions.\nPerformance Data Generation, Analytics and Visualization:\nDevelop frameworks and methodologies for large-scale performance data generation and analysis.\nCreate automated workflows for data collection, processing, correlation, and reporting.\nDevelop performance dashboards and visualization tools that simplify interpretation of complex performance data.\nDefine and track meaningful performance KPIs and architectural metrics.\nUtilize Python-based analysis frameworks to process large datasets and generate actionable insights.\nEnable efficient consumption of performance information by architects, designers, and engineering leadership.\nCross-Functional Technical Leadership and Stakeholder Engagement:\nPartner closely with architecture teams, performance stimulus generation teams, silicon design teams, and product stakeholders.\nDrive technical discussions related to performance methodology, architectural assumptions, workload behavior, scalability analysis, and bottleneck identification.\nReview architectural proposals and provide performance-driven feedback.\nPresent performance studies, technical findings, and architectural recommendations to engineering leadership.\nInfluence product and architecture decisions through data-backed analysis and sound engineering judgment.\nAct as a key technical bridge between architecture, modeling, and performance analysis organizations.\nMethodology Development and Team Growth:\nDrive improvements in modeling methodologies, simulation efficiency, and analysis workflows.\nIdentify opportunities for automation across modeling, validation, performance analysis, and reporting activities.\nEstablish best practices for model quality, performance characterization, and architectural analysis.\nContribute to technical mentoring and knowledge sharing across the team.\nSupport the development of junior engineers and future team growth initiatives.\nHelp cultivate a culture of technical excellence and continuous improvement.\nThe ideal candidate should show the following behavioral traits:\n\nStrong quantitative reasoning and data-driven decision-making skills. Analytical and Problem-Solving Skills\nStrong communication and collaboration skills.\nPresentation (technical) and stakeholder management skills.\nInfluence engineering decisions through rigorous analysis and technical credibility.\nOperate independently and deliver results in ambiguous problem spaces.\nIndependently solve complex technical problems.\nQualifications:\nMinimum qualifications, you must possess the below minimum qualifications to be initially considered for this position.\nBachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, Electronics Engineering.\n6+ years of industry experience in:\nPerformance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.\nSoC architecture, including on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.\nMemory subsystem architecture, including memory controllers, cache hierarchies, data movement, and latency/bandwidth characterization and performance bottleneck analysis.\nSoftware development experience in C++.\nWorking proficiency in Python for automation, performance analysis, data processing, and visualization.\nHands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.\nExperience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.\nPerforming architectural tradeoff analysis and performance debug and characterization studies.\n\n This position is not eligible for Intel immigration sponsorship.\nPreferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nDeep understanding of AI accelerator architectures and modern AI infrastructure.\nExperience modeling memory, communication, interconnect, or scalability-related subsystems.\nExperience with Network-on-Chip (NoC) architecture and interconnect performance analysis.\nUnderstanding of scale-up and scale-out architectures used in modern AI computing platforms.\nFamiliarity with AI/ML workloads, large language models, distributed training, and inference environments.\nExperience with performance stimulus generation methodologies and workload characterization.\nExperience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.\nExperience evaluating large-scale distributed AI systems and accelerator clusters.\nExperience mentoring engineers and providing technical leadership in cross-functional environments.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, California, Santa ClaraAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":11130,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-02T00:35:45Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,014 · green card filings: 487","filings_12m":2014,"filings_prev_12m":3001,"green_card_filings_12m":487,"median_offered_wage_usd":134579,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":728}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":3,"expected_fill_days":30,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/intel-ai-silicon-performance-modeling-and-analysis-engineer","json_url":"https://alion.io/job/intel-ai-silicon-performance-modeling-and-analysis-engineer.json","meta":{"generated_at":"2026-11-03T20:35:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3299,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-ai-silicon-performance-modeling-and-analysis-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-ai-silicon-performance-modeling-and-analysis-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-ai-silicon-performance-modeling-and-analysis-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-ai-silicon-performance-modeling-and-analysis-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-ai-silicon-performance-modeling-and-analysis-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3593962}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3593962},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}