{"id":3321860,"url":"https://alion.io/job/intel-ai-system-performance-architect","title":"AI System Performance Architect","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":96,"ghost_share":0.031,"stale_share":0.49,"repost_share":0.042,"time_to_fill_p50_days":30,"computed_at":"2026-10-31T05:58:55Z"}},"role":"DevOps","role_family":"DevOps","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":74000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":8},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"KV Cache","optional":false},{"name":"LLM","optional":false},{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"Quantization","optional":false},{"name":"SGLang","optional":false},{"name":"TPOT","optional":false},{"name":"vLLM","optional":false}],"status":"live","first_seen_at":"2026-10-26T00:00:00Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-10-31T00:05:27Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nAbout the Role\nWe are looking for a talented and motivated AI System Performance Architect. The role owns the end-to-end understanding of AI training and inference systems, sitting where serving strategy, parallelism, collective communication, and interconnect behavior come together. Through analytical modelling and multi-GPU simulation, the candidate translates SLA and deployment targets into concrete architectural guidance for Intel's future AI platforms. Strong analytical skills and the ability to present performance findings and configuration recommendations to engineering and leadership teams are essential.\nKey Responsibilities\nOwn end-to-end understanding of the AI training/inference system and build analytical models and multi-GPU simulation - including MPI/collective communication (allgather, allreduce, all-to-all) and interconnect contention - to project performance, expose architectural bottlenecks, and recommend optimal Intel system configurations.\nModel inferencing strategies - static batching, continuous batching, disaggregated serving, and chunked prefill - across frameworks such as vLLM and SGLang, covering agentic inferencing, prefix caching, and multi-turn flows.\nCover data, pipeline, tensor, and expert parallelism and their communication patterns.\nDrive studies against SLA targets - batch size, TTFT, TPOT, ISL/OSL, and TPS.\nAnalyse regression run traces and find patterns in utilization counters across SLA operating points to identify architectural bottlenecks.\nPerform what-if analysis by sweeping core count, memory/cache capacity and bandwidth, fabric bandwidth, GPU interconnect, and deployment options; deliver optimization and optimal architecture recommendations.\nScout whitepapers, blogs, and conferences; keep self and team updated on AI innovations applicable to Intel's end-to-end system.\nQualifications:\nRequired Qualifications\nBachelor's, master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nBachelors with 8+ yrs, master’s with 6+ years and Ph.D. with 3+ years of experience in system performance modelling, AI workload analysis, or hardware architecture.\nStrong proficiency in Python, with the ability to build modular, maintainable analytical models and simulation frameworks.\nSolid understanding of LLM inference and training mechanics: prefill vs. decode, KV cache, batching policies, and quantization.\nWorking knowledge of distributed parallelism strategies and their communication patterns.\nFamiliarity with multi-GPU interconnect architectures (NVLink, PCIe, CXL, or equivalent).\nUnderstanding of SoC and platform fundamentals: core count scaling, cache/memory capacity and bandwidth, and fabric behavior. Good-to-Have Skills\nExperience building discrete-event simulators for multi-node or multi-accelerator systems.\nFamiliarity with performance profiling tools (e.g., Intel VTune, NVIDIA Nsight, or similar).\nPrior experience in a semiconductor or hardware company working on AI accelerator or platform products. Join Intel and be part of a team that is shaping the future of data-driven innovation. Seize the opportunity to make a meaningful impact through your expertise and creativity-apply today.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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