{"id":3540164,"url":"https://alion.io/job/intel-analog-circuit-design-engineer-2","title":"Analog Circuit Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":90,"ghost_share":0.033,"stale_share":0.544,"repost_share":0.044,"time_to_fill_p50_days":30,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":50000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":843},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-29T00:00:00Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-11-02T16:59:46Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Job Details:\nJob Description:\nRole Overview\nAs an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance power management solutions directly integrated onto advanced processors (CPUs, GPUs, or SoCs). You will work at the intersection of Analog/Mixed-Signal IC design and Power Electronics to improve energy efficiency and performance in next-generation computing systems.\nKey Responsibilities\nCircuit Architecture and Design: Develop and refine analog topologies such as Operational Amplifiers (Op-Amps), Bandgap References, Data Converters (ADC/DAC), and Phase-Locked Loops (PLLs).\nDesign and Simulation: Perform transistor-level design using industry-standard tools (like Cadence Virtuoso). Conduct extensive Monte Carlo simulations, corner analysis, and noise analysis to ensure high yield and reliability.\nLayout Oversight: Collaborate closely with layout engineers to guide critical placement and routing, focusing on matching, shielding, and minimizing parasitic capacitance/resistance.\nVerification: Use SPICE-based simulators to verify circuit functionality against rigorous performance specifications (speed, power, gain, etc.).\nPost-Silicon Characterization: Bench-test silicon prototypes in the lab to validate performance against pre-silicon models and debug hardware anomalies\nQualifications:\nRequired Technical Skills\nTransistor Fundamentals: Expert knowledge of MOSFET/BJT device physics, small-signal modeling, and aging effects.\nEDA Tool Proficiency: Mastery of Cadence (Spectre/Virtuoso), Mentor Graphics, or Synopsys tool suites.\nSignal Integrity: Deep understanding of thermal noise, jitter, crosstalk, and power supply rejection ratio (PSRR).\nMixed-Signal Flow: Familiarity with Verilog-A or Verilog-AMS for behavioral modeling of analog blocks.\nQualifications\nEducation: BS, MS, or PhD in Electrical Engineering (EE) with a concentration in Analog IC Design.\nExperience: 3 - 7 years of experience in analog design (FinFET or planar CMOS nodes).\nAnalytical Mindset: Strong mathematical background for analyzing feedback systems and stability.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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