{"id":3328390,"url":"https://alion.io/job/intel-analog-circuit-design-engineer","title":"Analog Circuit Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":91,"ghost_share":0.033,"stale_share":0.505,"repost_share":0.044,"time_to_fill_p50_days":30,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":58000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-16T00:00:00Z","employer_posted_date":"2026-09-16","last_verified_at":"2026-10-29T02:31:34Z","board_verified":true,"closed_at":null,"days_open":43,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":43},"description":"Job Details:\nJob Description:\nIntel is looking for an experienced Analog Designer to join the IO Design Team in Bengaluru. In this role, you will be responsible for leading the design and development of advanced analog and mixed-signal circuits that enable high-speed chip-to-chip, package-to-package, and system-level connectivity for Intel's next-generation products.\nThe ideal candidate will have a strong background in transistor-level circuit design, high-speed IO architectures, and silicon debug. This position requires technical leadership, cross-functional collaboration, and ownership of critical IP blocks from concept through silicon validation.\nKey Responsibilities-\nLead the design, analysis, and optimization of analog and mixed-signal circuits for high-speed IO interfaces.\nDevelop and drive architecture and circuit implementation for:\nHigh-speed TX and RX circuits\nSerializer/Deserializer (SerDes) building blocks\nPLLs, DLLs, CDRs, and clocking circuits\nEqualization and signal conditioning circuits\nBandgap references, bias generation, and LDOs\nESD protection and IO pad circuitry\nPerform detailed transistor-level design, simulation, and verification across multiple PVT corners.\nDrive design closure for performance metrics including bandwidth, jitter, noise, power, area, yield, and reliability.\nCollaborate closely with physical design teams on layout reviews and post-lay out optimization.\nSupport silicon bring-up, characterization, root-cause analysis, and correlation between simulation and silicon measurements.\nWork with architecture, digital design, signal integrity, package, product engineering, and validation teams to ensure successful product execution.\nMentor junior engineers and contribute to team-wide design methodologies and best practices.\nDrive technical reviews and provide leadership in solving complex design challenges.\nQualifications:\nBachelor's or master's degree in electrical engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.\n5 to 9 years of industry experience in analog/mixed-signal IC design.\nStrong expertise in CMOS analog circuit design fundamentals.\nProven experience designing high-speed analog circuits in advanced technology nodes.\nHands-on experience with one or more of the following: SerDes architectures, High-speed IO interfaces, PLL/DLL/CDR circuits, TX/RX analog front-end circuits, Clock distribution networks, Reference and bias circuits, LDOs and power management circuits.\nDeep understanding of circuit noise, mismatch, jitter, stability, and reliability considerations.\nStrong experience with Cadence Virtuoso, Spectre, and industry-standard analog verification flows.\nExpertise in: Corner analysis, Monte Carlo simulations, Statistical design methodologies, post-layout verification and extraction analysis, Strong debugging and analytical problem-solving skills.\nExperience with industry-standard high-speed interfaces such as: PCI Express (PCIe), DDR Memory Interfaces, USB, Ethernet, MIPI, DP, eDP, HDMI, UCIe.\nExperience in advanced process technologies such as FinFET and Gate-All- Around (GAA) nodes.\nKnowledge of signal integrity, channel modelling, and equalization techniques.\nExperience in silicon validation and lab characterization.\nFamiliarity with reliability signoff, ESD verification, and EM/IR analysis.\nScripting experience using Python, Perl, TCL, or SKILL for design automation and productivity enhancement.\nKey Competencies\nTechnical leadership in analog and mixed-signal design.\nStrong communication and stakeholder management skills.\nAbility to work effectively in global, cross-functional environments.\nStructured problem-solving and decision-making capabilities.\nPassion for innovation and continuous improvement.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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