{"id":3593960,"url":"https://alion.io/job/intel-atom-cpu-layout-design-engineer-2","title":"Atom CPU Layout Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":101,"ghost_share":0.03,"stale_share":0.535,"repost_share":0.059,"time_to_fill_p50_days":30,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Zapopan, Mexico"],"countries":["MX"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":41000,"max_usd":99000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":769},"experience_years_min":1,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Synopsys Custom Compiler","optional":false},{"name":"Linux","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2026-11-01T00:00:00Z","employer_posted_date":"2026-11-01","last_verified_at":"2026-11-06T06:20:25Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nThe Role and Impact\nAs a Layout Design Engineer, you will play a critical role in the physical implementation of next-generation high-performance Intel Atom microprocessors. Your day-to-day responsibilities will include driving the design of memory compilers, custom IPs, and partitions that support CPU products. Your contributions will directly impact the efficiency and performance of Intel's cutting-edge technologies used globally.\nBusiness Group\nYou will join Intel Corporation's ATOM GDC Physical Design organization, which focuses on delivering innovative and efficient physical design solutions for Intel Atom microprocessors. This group supports Intel's broader mission to create world-class semiconductor products that empower cutting-edge computing technologies.\nResponsibilities will include but are not limited to\nPerform and drive complex physical design assignments independently, ensuring best practices and high efficiency.\nCollaborate closely with circuit design engineers to interpret schematics and enable successful physical implementation.\nLead physical design efforts ranging from leaf-level cell design to full partition integration.\nAssess and implement solutions for custom IPs and memory compilers to support high-performance CPU products.\nDevelop and optimize layout scripts, macros, and tools to enhance design implementation workflows.\nWork collaboratively with cross-functional teams across various Intel sites to align on design objectives.\nThe ideal candidate should show the following behavioral traits:\nGood English communication skills.\nQualifications:\nMinimum qualifications are required to be initially considered for this position .\nBachelor's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.\n6+ months of hands-on experience in:\nLayout design (experienced would be obtained through a combination, of relevant industry job experience, internship experience and/or schoolwork/classes/research).\nIndustry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar software.\n\nAdvanced English level.\nMust have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).\n Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMaster's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.\n1+ years of experience or familiarity with Very Large-Scale Integration (VLSI) or Complementary Metal-Oxide-Semiconductor (CMOS) logic circuit design.\nPractical knowledge of Unix/Linux operating systems.\nRequirements listed would be obtained through a combination of relevant industry job experience, internship experience and/or schoolwork/classes/research.\nWe invite you to bring your creativity and technical expertise to Intel, where you'll contribute to shaping the future of computing technologies.\nYour journey starts applying today and be part of Intel's innovation legacy.\nJob Type:\nExperienced HireShift:\nShift 1 (Mexico)Primary Location:\nMexico, GuadalajaraAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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