{"id":1424448,"url":"https://alion.io/job/intel-corporation-aiml-cad-engineer-rtl-design-verification","title":"AI/ML CAD Engineer, RTL & Design Verification","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":83,"ghost_share":0.036,"stale_share":0.518,"repost_share":0.048,"time_to_fill_p50_days":30,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Hillsboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":111000,"max_usd":213000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":664},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CI/CD","optional":false},{"name":"C++","optional":true},{"name":"Claude Code","optional":true},{"name":"Copilot","optional":true},{"name":"Cursor","optional":true},{"name":"GitHub","optional":true},{"name":"Linux","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-28T23:17:24Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-27T19:23:25Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"Job Details:\nJob Description:\nThe Role and Impact\nJoin a team helping shape the future of high-performance CPU design. As an AI/ML CAD Engineer supporting RTL and Design Verification, you will develop and enhance automation, tools, and methodologies that help engineering teams design and validate advanced microprocessors.\nYou will combine software engineering, CAD/EDA, RTL and verification knowledge, and AI-assisted development to improve front-end design workflows spanning RTL development, simulation, verification, emulation, static sign-off, and CI/CD.\nThis is an opportunity to apply strong programming and problem-solving skills to complex CPU development challenges while helping introduce AI-enabled capabilities that improve engineering productivity and efficiency.\nWhat You'll Do\nKey responsibilities will include but not limited to:\nTroubleshoot issues across RTL, EDA Frontend tools (VC_SPYGLASS(Lint, CDC and RDC), VCS, VMS) and automation infrastructure, and design environments.\nDevelop, deploy, and maintain AI-assisted CAD/EDA automation, tools, and workflows supporting RTL design and verification.\nBuild scripts and software solutions that improve RTL build, simulation, verification, emulation, regression, and static sign-off workflows.\nApply AI/ML and AI-assisted development technologies to improve engineering automation, debugging, and productivity.\nDevelop and enhance CI/CD and regression automation for hardware development workflows.\nAnalyze workflow and infrastructure data to identify opportunities for improved performance, reliability, and engineering efficiency.\nPartner with engineering and cloud infrastructure teams to improve compute utilization and scalability.\nCollaborate with RTL design, verification, CAD, infrastructure teams, and EDA vendors to resolve technical issues and improve methodologies.\nBehavioral traits that we are looking for:\nTechnical curiosity: Enjoys learning new technologies and finding better ways to solve engineering challenges.\nProblem solving: Uses structured analysis and sound judgment to troubleshoot complex technical issues.\nCollaboration: Works effectively across design, verification, software, infrastructure, and vendor teams.\nCommunication: Clearly communicates technical issues, recommendations, and solutions to different audiences.\nOwnership: Takes responsibility for deliverables and follows issues through resolution.\nAdaptability: Comfortable learning and working across evolving AI, software, and semiconductor design technologies.\nIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.\n See Intel Benefits for more details. \nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\nNote:\nFor information on Intel’s immigration sponsorship guidelines, please see\nIntel U.S. Immigration Sponsorship Information\nMinimum Qualifications and Experience:\nBachelor's in Electrical or Computer Engineering or Computer Science + 3+ years of experience, or a Master's in the same field with 1+ years of educational or work experience.\nYour experience describe above must be in the following:\nLinux experience with shell scripting.\nPython, Perl, or C/C++ skills\nRTL/Verification CAD tools\nDebugging across RTL, automation flows, and software/tool interactions.\nPreferred Qualifications and Experience:\nTroubleshoot EDA tools and design environments\nExperience with major EDA tools (VC_SpyGlass, VCS, Questasim, coverage/low-power tools).\nExperience with CAD/EDA automation (simulation/emulation flows, verification integration, CI/CD).\nExperience with AI Development environments such as GitHub/Copilot, Claude Code, Cursor.\nExperience supporting RTL build and simulation/verification workflows.\nExperience working with EDA vendors (issue triage, features, debugging).\nMulti-domain debugging (RTL, testbench, tools, scripts, infrastructure).\nCloud compute experience (scaling sim farms, resource optimization).\nDevOps for hardware (regressions, CI/CD, monitoring/alerting).\nVerilog/SystemVerilog.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Texas, AustinAdditional Locations:\nUS, Oregon, HillsboroPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":6499,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-28T23:17:24Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,014 · green card filings: 487","filings_12m":2014,"filings_prev_12m":3001,"green_card_filings_12m":487,"median_offered_wage_usd":134579,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":728}],"liveness":{"score":41,"band":"fade","label":"Fading","p_open":1,"p_active":0.552,"p_room":0.75,"age_days":28,"expected_fill_days":30,"reasons":["conf:0","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-aiml-cad-engineer-rtl-design-verification","json_url":"https://alion.io/job/intel-corporation-aiml-cad-engineer-rtl-design-verification.json","meta":{"generated_at":"2026-10-27T23:38:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15850,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-aiml-cad-engineer-rtl-design-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-aiml-cad-engineer-rtl-design-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-aiml-cad-engineer-rtl-design-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-aiml-cad-engineer-rtl-design-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-aiml-cad-engineer-rtl-design-verification"}]}