{"id":827136,"url":"https://alion.io/job/intel-corporation-design-verification-engineer-2","title":"Design Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":101,"ghost_share":0.02,"stale_share":0.584,"repost_share":0.04,"time_to_fill_p50_days":27,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":107000,"max_usd":208000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":468},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Linux","optional":true},{"name":"Siemens ModelSim","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-11T00:00:00Z","employer_posted_date":"2026-09-11","last_verified_at":"2026-10-18T16:21:57Z","board_verified":true,"closed_at":null,"days_open":39,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":39},"description":"Job Details:\nJob Description:\nAbout Intel & Silicon Chassis\nIntel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification of next-generation interconnect and chassis IPs that underpin Intel's most ambitious SoC and platform products.\nPosition Overview\nYou will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures - developing end-to-end verification skills from day one.\nWe look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work. You do not need to know everything on day one; you do need strong fundamentals, genuine curiosity, and the drive to ramp fast.\nKey Responsibilities\nDevelop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers\nWrite, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups\nContribute to functional coverage plans, coverage closure analysis, and regression triage\nParticipate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries\nUse AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting\nContinuously build depth in hardware design, verification methodology, and the chip development flow\nWhat We're Looking For\nYou should demonstrate the following professional traits to be successful:\nGenuine curiosity and the drive to ramp fast\nAlgorithmic thinking with a commitment to writing clean code\nEnthusiasm for applying the latest AI-assisted development tools as a core part of how you work\nQualifications:\nThis position is not eligible for Intel immigration sponsorship.\nMinimum Qualifications\nBS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 3+ months of Internship experience in a hardware design or verification environment\nFoundation in logic design and digital circuits - required; ability to read and reason about RTL is essential\nDemonstrated algorithmic thinking and software fundamentals application - required\nDemonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships\nCoursework or project exposure to two or more of the following: computer architecture, parallel and distributed computing, operating systems, hardware/software interfaces, VLSI design\nDemonstrated use of AI coding assistants as a regular part of coursework or project work - not occasional use, but as a genuine productivity tool\nPreferred Qualifications\nCoursework or project work in hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa, or similar)\nExposure to SystemVerilog, UVM concepts, or assertion-based verification through coursework, self-study, or internship\nFamiliarity with standard bus protocols (AXI, AHB, PCIe) or cache/memory hierarchy concepts\nDemonstrated project work (senior design, research, hackathon, personal) involving hardware modeling, algorithm implementation in HDL, or hardware-software co-design\nComfort working in Linux environments, using version control (git), and writing build/test automation scripts\nWorked experience in any related field\nJob Type:\nCollege GradShift:\nShift 1 (United States of America)Primary Location:\nUS, California, Santa ClaraAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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