{"id":2284419,"url":"https://alion.io/job/intel-corporation-e-core-atom-cpu-layout-design-engineer-2","title":"E-Core (Atom) CPU Layout Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":91,"ghost_share":0,"stale_share":0.527,"repost_share":0.044,"time_to_fill_p50_days":27,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia","Kulim, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":42000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":712},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Unix","optional":false}],"status":"live","first_seen_at":"2026-10-07T00:00:00Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-12T19:26:01Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nAs an E-Core (Atom) CPU Layout Design Engineer, you will be part of a highly skilled team responsible for the design of future generation, high-performance Intel Atom microprocessors. In this role, you will drive the physical implementation of a variety of memory compilers, custom IP blocks, and layout partitions that directly support Intel's CPU products.\nYou will work in a dynamic environment where design challenges are complex, assignments are broadly defined, and solutions often require creativity, deep technical knowledge, and strong problem-solving skills.\nYour responsibilities will include, but will not be limited to:\n- Independently assess and drive complex digital physical design assignments across multiple design stages.\n- Work closely with circuit design engineers to interpret schematics and drive physical implementation.\n- Work interactively and proactively with our CAD team to debug tool functionality and bugs.\n- Build and verify all levels of physical design hierarchy from leaf-level cell layout to block-level and top-level integration.\n- Partnering with SoC teams and cross site design groups to ensure alignment, reuse, and consistency across projects.\nIn addition to the qualifications below the ideal candidate will also have the following:\n-Excellent verbal and written communication skills.\n-Excellent interpersonal skills.\n-Prioritization and multitasking skills.\n-Good analytical and problem-solving skills\nQualifications:\nMinimum Qualifications:\n- Candidate must possess a Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.\n- 3+ years of experience in layout design.\nAdditional qualifications include: \n- less than 2 years of experience in layout design for grade 3.\n- Familiarity with Very Large Scale of Integration VLSI and Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design.\n- Proficient programming skills UNIX shell script TCL Perl.\nJob Type:\nExperienced HireShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nMalaysia, KulimPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":3299,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"Malaysia","iso":"MY","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-11T13:05:21Z"}],"visa":[],"liveness":{"score":59,"band":"ok","label":"Likely open","p_open":1,"p_active":0.593,"p_room":1,"age_days":5,"expected_fill_days":27,"reasons":["conf:0","stale_co","win:early","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-e-core-atom-cpu-layout-design-engineer-2","json_url":"https://alion.io/job/intel-corporation-e-core-atom-cpu-layout-design-engineer-2.json","meta":{"generated_at":"2026-10-12T23:20:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":38316,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-e-core-atom-cpu-layout-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-e-core-atom-cpu-layout-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-e-core-atom-cpu-layout-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-e-core-atom-cpu-layout-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-e-core-atom-cpu-layout-design-engineer-2"}]}