{"id":1424446,"url":"https://alion.io/job/intel-corporation-ip-design-verification-engineer-3","title":"IP Design Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":101,"ghost_share":0.02,"stale_share":0.584,"repost_share":0.04,"time_to_fill_p50_days":27,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States","Folsom, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":226000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":568},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-28T23:17:24Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-18T16:21:57Z","board_verified":true,"closed_at":null,"days_open":20,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":20},"description":"Job Details:\nJob Description:\nAbout the Role\nJoin our Logic Design and Validation group within the Design Technology Platforms department, where you'll play a key role in shaping the future of semiconductor technology. You'll be part of a dynamic team responsible for developing RTL models and pre-silicon validation tests for test chips on next-generation silicon manufacturing processes. This is an opportunity to work at the cutting edge of chip design, collaborating across multidisciplinary teams to deliver robust, high-quality silicon.\nWhat You'll Do\nWhat You'll Do\nDesign & Develop Verification Environments - Build and maintain scalable, reusable UVM-based testbenches and test cases for complex mixed-signal CMOS designs at the block, subsystem, and SoC levels.\nDefine Verification Strategy - Own and drive comprehensive verification plans for complex digital systems, ensuring thorough coverage closure across multiple projects.\nRTL Development & Integration - Develop RTL designs and integrate logic components into SoC architectures, collaborating with IP providers to validate IPs at the system level.\nPower Methodology - Develop and implement power verification methodologies for complex mixed-signal IPs using industry-standard frameworks.\n Assertion-Based Verification - Create and apply SystemVerilog Assertions (SVA) to strengthen coverage closure and improve overall verification quality.\nDebug & Root Cause Analysis - Identify, debug, and resolve pre-silicon failures, implementing corrective measures and driving issues to closure.\nCross-Team Collaboration - Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies for complex architectural features.\nContinuous Improvement - Incorporate post-silicon learnings and feedback into enhanced pre-silicon verification methodologies.\nDocumentation & Reviews - Maintain detailed test plans and lead technical reviews with design and architecture teams.\nBehavioral Traits\nSelf-motivated with a strong sense of urgency and commitment to delivering results.\nExcellent communication and interpersonal skills with the ability to work effectively across teams.\nStrong analytical and troubleshooting skills with a structured approach to problem-solving.\nClear and concise documentation and presentation abilities.\nQualifications:\nThe Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications\nOption A: Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience.\n Option B: Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 3+ years of relevant experience.\nExperience with Pre-silicon logic validation using SystemVerilog and UVM.\nExperience in Digital design using Verilog and/or SystemVerilog.\nExperience with pre-silicon validation closure across multiple projects.\nHands-on experience with UVM testbench design, with a focus on reusability and scalability.\nExperience with end-to-end validation strategies for complex digital systems.\nExperience with SystemVerilog Assertions (SVA) for coverage closure.\nExperience with coverage-driven verification methodologies.\nScripting proficiency in Python, Perl, or TCL for design and verification automation.\n\nPreferred Qualifications\nExperience in Mixed-Signal IP verification (e.g., PLL, DDR, SerDes).\nExperience with Unified Power Format (UPF) specification and power-aware verification.\nExperience with synthesizable Verilog/SystemVerilog and industry-standard simulation tools.\nExperience with timing and power convergence tools and methodologies.\nExperience with AI/ML techniques and their application in verification automation and efficiency.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nUS, California, FolsomPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":6203,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-28T23:17:24Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,014 · green card filings: 487","filings_12m":2014,"filings_prev_12m":3001,"green_card_filings_12m":487,"median_offered_wage_usd":134579,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":728}],"liveness":{"score":41,"band":"fade","label":"Fading","p_open":1,"p_active":0.548,"p_room":0.75,"age_days":20,"expected_fill_days":27,"reasons":["conf:13","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-ip-design-verification-engineer-3","json_url":"https://alion.io/job/intel-corporation-ip-design-verification-engineer-3.json","meta":{"generated_at":"2026-10-19T17:56:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13824,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-ip-design-verification-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-ip-design-verification-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-ip-design-verification-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-ip-design-verification-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-ip-design-verification-engineer-3"}]}