{"id":102547,"url":"https://alion.io/job/intel-corporation-ip-rtl-senior-design-engineer","title":"IP RTL Senior Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":96,"ghost_share":0.031,"stale_share":0.594,"repost_share":0.042,"time_to_fill_p50_days":30,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":60000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-07-29T00:00:00Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-11-04T22:35:36Z","board_verified":true,"closed_at":null,"days_open":99,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":98},"description":"Job Details:\nJob Description:\nThe Role and Impact:\nAs an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Define and implement range-based access control for secured memory and register paths across HBW and LBW. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Define fault behavior for unauthorized accesses and corrupt transactions, including silent block semantics, RAZWI-style handling, poison propagation, and timeout cleanup. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Support error injection, diagnostics, and post-silicon debug hooks for both security and reliability validation. Define and implement telemetry capture for fabric load, latency, congestion, error context, and other operational health indicators. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Integrate trigger, monitor, and logging hooks needed for bring-up, stress triage, and post-silicon correlation. Work with architecture, validation, firmware, and post-silicon teams to ensure telemetry and debug signals are useful, stable, and diagnosable. Balance observability depth against area, timing, bandwidth, and survivability constraints. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.\nKey Responsibilities:\nDevelop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.\nDefine architecture and microarchitecture features for the IP block being designed.\nApply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.\nStrong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.\nExperience with secure MMIO, access-control/firewall logic, or privilege-based filtering.\nExperience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.\nSupport SoC customers with seamless integration and verification of IP blocks.\nTelemetry and debug are both observability functions rather than primary Datapath functions.\nDrive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.\nQualifications:\nMinimum Qualifications:\nBachelor's degree in electrical engineering, Computer Engineering, or related field.\nA minimum of 8 years of experience in logic design and RTL development.\nProficiency in hardware description languages such as Verilog, System Verilog.\nStrong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.\nExperience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).\nKnowledge of IP block integration workflows within SoC designs.\nExpertise in RAS/debug/security/telemetry.\nPreferred Qualifications:\nMaster's or PhD degree in Electrical Engineering, Computer Engineering, or related field.\n10+ years of professional experience encompassing complex IP logic design for high-performance applications.\nDemonstrated expertise in architecture and microarchitecture definition.\nFamiliarity with advanced verification methodologies such as UVM or formal verification techniques.\nStrong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.\nA mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.\nTake the next step in your career and become part of Intel's world-class engineering team, shaping the future of technology with groundbreaking innovations. Apply today to make an impact.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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