{"id":1524856,"url":"https://alion.io/job/intel-corporation-mid-level-physical-design-engineer-cpu-2","title":"Mid-level Physical Design Engineer CPU","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":86,"open_postings":92,"ghost_share":0,"stale_share":0.543,"repost_share":0.043,"time_to_fill_p50_days":27,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":88000,"max_usd":163000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":3384},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Perl","optional":true},{"name":"Ruby","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-09-29T00:00:00Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-13T14:19:01Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"Job Details:\nJob Description:\nAbout the Role\nJoin a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Mid-level Physical Design Engineer CPU, you will contribute todelivering high-performance, power-efficient silicon using advanced process technologies.\nIn this role, you will take on increasing ownership within the RTL-to-GDS flow, working on block-level implementation while collaborating closely with cross-functional teams. This position offers strong growth opportunities as you build depth in physical design and SoC development.\nWhat You’ll Do\nKey responsibilities will include but not limited to:\nExecute physical design implementation for CPU core blocks or subsystems\nPerform synthesis, floor planning, place and route (PnR), and design closure activities\nConduct static timing analysis (STA), power analysis, and physical verification\nIdentify and debug timing, power, and design rule violations\nContribute to achieving timing, power, and area (PPA) targets\nDevelop and maintain scripts for design automation (e.g., TCL, Python)\nCollaborate with RTL design, verification, clocking, and full-chip teams\nSupport improvements to design flows, methodologies, and best practices\nDocument technical work and share knowledge within the team\nBehavioral traits that we are looking for:\nStrong analytical and problem-solving skills\nTakes ownership of assigned tasks and delivers with accountability\nWorks effectively in collaborative, cross-functional environments\nCommunicates technical information clearly and concisely\nShows adaptability in a fast-paced, evolving engineering environment\nDemonstrates continuous learning and skill development\nWhy Join Us\nWork on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide\nBe part of a team driving innovation at advanced semiconductor process nodes\nContribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design\nCollaborate with experienced engineers across architecture, design, and full-chip integration\nGrow your technical expertise through challenging problems, modern tools, and continuous learning opportunities\nJoin a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology\nIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. \n\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nNote:\nFor information on Intel’s immigration sponsorship guidelines, please see\nIntel U.S. Immigration Sponsorship Information\nMinimum Qualifications and Experience:\nBachelors in Computer / Electrical Engineering or related field with 5+ years of relevant work experience. Or a Masters in the same field with 3+ years of relevant work experience.\nYour experience described above must be in the following:\nExperience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure\nPV convergence (including static timing and power analysis)\nChip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks\nScripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)\nExperience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP\nPreferred Qualifications and Experience:\nIndustry experience/exposure with CPU Micro-Architecture\nPhysical design best known practices concerning floor-planning, routing techniques, clock distribution\nStatic Timing Analysis, Noise analysis, and reliability verification techniques\nRTL to GDS methodologies and formal equivalence\nSynopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":6107,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning","Growth opportunities"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-30T13:40:13Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,014 · green card filings: 487","filings_12m":2014,"filings_prev_12m":3001,"green_card_filings_12m":487,"median_offered_wage_usd":134579,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":53,"band":"ok","label":"Likely open","p_open":1,"p_active":0.59,"p_room":0.9,"age_days":14,"expected_fill_days":27,"reasons":["conf:10","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-mid-level-physical-design-engineer-cpu-2","json_url":"https://alion.io/job/intel-corporation-mid-level-physical-design-engineer-cpu-2.json","meta":{"generated_at":"2026-10-13T22:01:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33689,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-mid-level-physical-design-engineer-cpu-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-mid-level-physical-design-engineer-cpu-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-mid-level-physical-design-engineer-cpu-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-mid-level-physical-design-engineer-cpu-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-mid-level-physical-design-engineer-cpu-2"}]}