{"id":2284394,"url":"https://alion.io/job/intel-corporation-pre-silicon-soc-validation-technical-lead","title":"Pre-Silicon SoC Validation - Technical Lead","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":32000,"max_usd":72000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Shift-Left Security","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-08T00:00:00Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-24T03:51:18Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"Job Details:\nJob Description:\nRole Summary:\nSeeking an experienced SoC Validation Engineer to define, drive, and execute validation strategies across the full silicon lifecycle, from architecture definition and pre-silicon planning through silicon power-on, post-silicon debug, stepping readiness, and PRQ quality convergence.\nThe role requires deep expertise in complex SoC validation, security validation, coherency flows, firmware and hardware interaction, disaggregated architecture, and cross-functional technical leadership.\nThe engineer will be responsible for ensuring early risk identification, high-quality milestone readiness, predictable silicon bring-up, rapid sighting debug, and continuous feedback from post-silicon learnings into earlier validation phases.\nKey Responsibilities:\nDefine and drive end-to-end SoC validation strategy across the full lifecycle, including architecture definition, pre-silicon validation planning, RTL milestone readiness, silicon power-on preparation, post-silicon debug, stepping readiness, and PRQ quality convergence.\nDevelop comprehensive validation plans, execution strategies, coverage goals, debug plans, and sign-off criteria aligned to program milestones and product quality targets.\nDrive validation of critical SoC flows across security, coherency, memory, fabric, IO, and cross-die interactions in disaggregated architectures.\nValidate complex hardware, firmware, and software interactions with specific focus on security handshakes, coherency protocols, cache and fabric ordering, access control, isolation, attestation, fuse/security policy behavior, and multi-die/domain interactions.\nReview architecture and microarchitecture specifications to identify validation gaps in security, coherency, shared-resource behavior, cross-die communication, firmware sequencing, and lifecycle readiness from pre-silicon through post-silicon execution.\nDrive debug of complex pre-silicon and post-silicon failures, identify root cause across RTL, firmware, microcode, platform software, validation content, security policy, coherency behavior, and system-level configuration.\nPartner with architecture, design, verification, firmware, post-silicon, security, coherency, platform, manufacturing, and program teams to ensure high-quality validation readiness, silicon bring-up efficiency, and timely closure of issues across product milestones.\nUse post-silicon sightings, customer issues, stepping feedback, defect trends, security observations, and coherency escapes to strengthen earlier validation strategies, improve coverage, and prevent repeated escapes across programs.\nDefine validation quality metrics, execution dashboards, risk indicators, milestone readiness reports, and sign-off recommendations for leadership reviews.\nDrive innovation in validation efficiency, including automation, test grading, coverage-driven execution, AI/ML-assisted bug hunting, regression optimization, and shift-left methodologies.\nMentor senior and mid-level engineers, build technical depth in the team, and contribute to reusable validation methodologies, collateral, and best practices across programs.\nQualifications:\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, Embedded Systems, Computer Science, or a related discipline.12-20 years of relevant industry experience in pre-silicon validation, SoC validation, design verification, silicon validation, firmware validation, or hardware/software co-validation.\nStrong understanding of SoC architecture, microarchitecture, CPU/core integration, fabrics, memory subsystem, security, coherency, cache hierarchy, firmware-driven security flows, and disaggregated/multi-die architectures.\nHands-on experience defining and executing validation strategies across the product lifecycle, including architecture review, pre-silicon planning, RTL milestone readiness, silicon power-on preparation, post-silicon sighting debug, stepping feedback, and PRQ quality convergence.\nProven experience in developing validation plans, test strategies, debug methodologies, coverage closure plans, post-silicon feedback loops, and milestone sign-off criteria for complex SoCs and disaggregated silicon products.\nRequired Technical Skills:\nDeep knowledge of SoC architecture, system architecture, disaggregated and multi-die architecture, microarchitecture fundamentals, IP/subsystem integration, fabrics, memory hierarchy, and cross-die communication.\nStrong expertise in validation methodologies across the pre-silicon to post-silicon continuum, including test planning, content development, coverage closure, milestone readiness, silicon bring-up support, sighting reproduction, and lifecycle feedback loops.\nStrong technical depth in security validation, coherency validation, cache/fabric ordering, access-control flows, isolation mechanisms, firmware-authenticated flows, fuse/security policy behavior, and multi-domain system interactions.\nStrong debug skills using waveform analysis, logs, traces, checkers, assertions, firmware instrumentation, and platform-level debug tools.\nExperience with one or more programming or scripting languages such as C, C++, Python, Perl, SystemVerilog, UVM, or similar validation automation languages.\nKnowledge of firmware and microcode flows, manageability firmware, or other SoC firmware interactions.\nUnderstanding of validation quality metrics, functional coverage, test effectiveness, regression health, bug trends, and milestone readiness indicators.\nLeadership and Collaboration Expectations\nOperate as a senior technical leader who can independently define technical direction, influence stakeholders, and drive convergence across multiple teams.\nLead cross-functional discussions with architecture, design, verification, firmware, post-silicon, platform, manufacturing, and program management teams.\nIdentify program risks early, propose mitigation plans, and drive technical decision-making to protect milestone predictability and product quality.\nCommunicate complex technical issues clearly through reviews, dashboards, status reports, debug summaries, and leadership updates.\nMentor engineers, build validation capability within the organization, and help establish scalable processes for future SoC programs.\nPreferred Qualifications:\nPrior Intel Xeon product validation experience across one or more server SoC generations, including pre-silicon planning, silicon power-on, post-silicon debug, stepping readiness, or PRQ quality convergence.\nExposure to Cheetah-based validation methodologies, including validation environment integration, filelist/dependency setup, methodology quality checks, simulation build/run readiness, or SoC/IP integration collateral checks.\nExposure to security, coherency, cache hierarchy, fabric, memory validation.\nExperience with lifecycle-driven validation improvements, including shift-left strategies, post-silicon sighting reproduction in pre-silicon environments, reusable validation content, formal-assisted validation, collateral consistency checks, and AI/ML-driven validation efficiency improvements.\nPrior experience driving A0/TI readiness, milestone sign-off, or post-silicon sighting reproduction in pre-silicon environments.\nDemonstrated ability to deliver results through ambiguity, influence without authority, and enable technical convergence across distributed teams.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":8679,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-11T13:05:21Z"}],"visa":[],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.607,"p_room":0.9,"age_days":17,"expected_fill_days":30,"reasons":["conf:25","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-pre-silicon-soc-validation-technical-lead","json_url":"https://alion.io/job/intel-corporation-pre-silicon-soc-validation-technical-lead.json","meta":{"generated_at":"2026-10-25T16:38:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24021,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-pre-silicon-soc-validation-technical-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-pre-silicon-soc-validation-technical-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-pre-silicon-soc-validation-technical-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-pre-silicon-soc-validation-technical-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-pre-silicon-soc-validation-technical-lead"}]}